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e86949f5a2
NVDEC falcon base address was being set without invoking hal api. Remove FALCON_NVDEC_BASE. This patch defines gpu_ops.fb.falcon_base_addr hal api to get this base address. Currently gp106 and tu104 have these implemented. gv100 uses the gp106 hal interface. Also, don't initialize the base for non-supported falcons. JIRA NVGPU-1587 Change-Id: I0be759b8462ede9b85690a70431480afdee9602c Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1969427 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
31 lines
1.3 KiB
C
31 lines
1.3 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "nvdec_tu104.h"
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#include <nvgpu/hw/tu104/hw_pnvdec_tu104.h>
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u32 tu104_nvdec_falcon_base_addr(void)
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{
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return pnvdec_falcon_irqsset_r(0);
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}
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