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89660dbd62
MISRA rule 14.4 doesn't allow the usage of integer types as booleans in the controlling expression of an if statement or an iteration statement. Fix violations where the result of a bitwise operation is used as a boolean in the controlling expression of if and loop statements. JIRA NVGPU-1020 Change-Id: If910150072c3dd67c31fe9819c3a9e738fd3c1c6 Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1932389 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
/*
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* Pascal GPU series Copy Engine.
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*
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* Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "ce_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_ce_gp10b.h>
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static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
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{
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nvgpu_log(g, gpu_dbg_intr, "ce blocking pipe interrupt\n");
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return ce_intr_status_blockpipe_pending_f();
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}
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static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr)
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{
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nvgpu_log(g, gpu_dbg_intr, "ce launch error interrupt\n");
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return ce_intr_status_launcherr_pending_f();
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}
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void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
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u32 clear_intr = 0;
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nvgpu_log(g, gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id);
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/* clear blocking interrupts: they exibit broken behavior */
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if ((ce_intr & ce_intr_status_blockpipe_pending_f()) != 0U) {
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clear_intr |= ce_blockpipe_isr(g, ce_intr);
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}
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if ((ce_intr & ce_intr_status_launcherr_pending_f()) != 0U) {
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clear_intr |= ce_launcherr_isr(g, ce_intr);
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}
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gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr);
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return;
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}
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u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ops = 0;
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u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id));
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nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id);
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if ((ce_intr & ce_intr_status_nonblockpipe_pending_f()) != 0U) {
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gk20a_writel(g, ce_intr_status_r(inst_id),
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ce_intr_status_nonblockpipe_pending_f());
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ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE |
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GK20A_NONSTALL_OPS_POST_EVENTS);
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}
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return ops;
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}
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