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e424e4791a
-Renamed and moved nvgpu_pmu_perf struct from public to unit specific -Renamed all functions as per public/private format NVGPU-5029 Change-Id: If3f479bb1443850a5c8a8714cd1c9da346cb566a Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300609 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/*
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* general clock structures & definitions
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*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CHANGE_SEQ_H
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#define NVGPU_CHANGE_SEQ_H
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#include "ucode_perf_change_seq_inf.h"
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#define SEQ_SCRIPT_CURR 0x0U
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#define SEQ_SCRIPT_LAST 0x1U
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#define SEQ_SCRIPT_QUERY 0x2U
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struct change_seq_pmu_script {
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struct perf_change_seq_pmu_script buf;
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u32 super_surface_offset;
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};
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struct change_seq {
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u8 version;
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bool b_enabled_pmu_support;
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u32 thread_seq_id_last;
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u64 thread_carry_over_timens;
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struct ctrl_perf_change_seq_change last_pstate_values;
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struct boardobjgrpmask_e32 clk_domains_exclusion_mask;
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struct boardobjgrpmask_e32 clk_domains_inclusion_mask;
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u32 client_lock_mask;
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};
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struct change_seq_pmu {
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struct change_seq super;
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bool b_lock;
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bool b_vf_point_check_ignore;
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u32 cpu_adverised_step_id_mask;
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u32 cpu_step_id_mask;
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u32 event_mask_pending;
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u32 event_mask_received;
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u32 last_completed_change_Seq_id;
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struct change_seq_pmu_script script_curr;
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struct change_seq_pmu_script script_last;
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struct change_seq_pmu_script script_query;
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u32 change_state;
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s64 start_time;
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s64 stop_time;
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};
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int perf_change_seq_sw_setup(struct gk20a *g);
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int perf_change_seq_pmu_setup(struct gk20a *g);
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#endif /* NVGPU_CHANGE_SEQ_H */
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