mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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e1200259ba
- QNX is pulling dgpu code from linux which has multiple build failure on QNX. Like QNX needs explicit declaration for all non-static functions. Some linux specific headers need to be put under __KERNEL__ flag. Change-Id: I15af1a1f6a069c82f9a81449f4f7c7d48612de42 Signed-off-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665752 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
97 lines
3.0 KiB
C
97 lines
3.0 KiB
C
/*
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* GV100 PMU
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include "gk20a/gk20a.h"
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#include "gv100/pmu_gv100.h"
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int gv100_pmu_init_acr(struct gk20a *g)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct nv_pmu_rpc_struct_acr_init_wpr_region rpc;
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int status = 0;
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memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_acr_init_wpr_region));
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rpc.wpr_regionId = 0x1;
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rpc.wpr_offset = 0x0;
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PMU_RPC_EXECUTE(status, pmu, ACR, INIT_WPR_REGION, &rpc, 0);
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if (status) {
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nvgpu_err(g, "Failed to execute RPC status=0x%x",
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status);
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}
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return status;
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}
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int gv100_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons rpc;
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u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
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int status = 0;
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if (falconidmask == 0)
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return -EINVAL;
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if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) |
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(1 << LSF_FALCON_ID_GPCCS)))
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return -EINVAL;
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g->pmu_lsf_loaded_falcon_id = 0;
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/* check whether pmu is ready to bootstrap lsf if not wait for it */
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if (!g->pmu_lsf_pmu_wpr_init_done) {
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pmu_wait_message_cond(&g->pmu,
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gk20a_get_gr_idle_timeout(g),
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&g->pmu_lsf_pmu_wpr_init_done, 1);
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/* check again if it still not ready indicate an error */
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if (!g->pmu_lsf_pmu_wpr_init_done) {
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nvgpu_err(g, "PMU not ready to load LSF");
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status = -ETIMEDOUT;
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goto exit;
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}
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}
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memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons));
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rpc.falcon_id_mask = falconidmask;
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rpc.flags = flags;
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rpc.falcon_va_mask = 0;
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rpc.wpr_base_virtual.lo = 0;
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rpc.wpr_base_virtual.hi = 0;
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PMU_RPC_EXECUTE(status, pmu, ACR, BOOTSTRAP_GR_FALCONS, &rpc, 0);
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if (status) {
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nvgpu_err(g, "Failed to execute RPC, status=0x%x", status);
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goto exit;
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}
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pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
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&g->pmu_lsf_loaded_falcon_id, 1);
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if (g->pmu_lsf_loaded_falcon_id != 1)
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status = -ETIMEDOUT;
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exit:
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return status;
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}
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