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17486ec1f6
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct channel_gk20a to struct nvgpu_channel Jira NVGPU-3248 Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2112424 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
124 lines
3.5 KiB
C
124 lines
3.5 KiB
C
/*
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* GK20A graphics fifo (gr host)
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*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef FIFO_GK20A_H
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#define FIFO_GK20A_H
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#include <nvgpu/types.h>
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#include <nvgpu/kref.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/runlist.h>
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#include <nvgpu/profile.h>
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struct nvgpu_channel;
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struct nvgpu_tsg;
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struct nvgpu_fifo {
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struct gk20a *g;
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unsigned int num_channels;
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unsigned int runlist_entry_size;
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unsigned int num_runlist_entries;
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unsigned int num_pbdma;
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u32 *pbdma_map;
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struct nvgpu_engine_info *engine_info;
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u32 max_engines;
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u32 num_engines;
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u32 *active_engines_list;
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/* Pointers to runlists, indexed by real hw runlist_id.
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* If a runlist is active, then runlist_info[runlist_id] points
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* to one entry in active_runlist_info. Otherwise, it is NULL.
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*/
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struct nvgpu_runlist_info **runlist_info;
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u32 max_runlists;
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/* Array of runlists that are actually in use */
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struct nvgpu_runlist_info *active_runlist_info;
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u32 num_runlists; /* number of active runlists */
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#ifdef CONFIG_DEBUG_FS
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struct {
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struct nvgpu_profile *data;
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nvgpu_atomic_t get;
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bool enabled;
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u64 *sorted;
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struct nvgpu_ref ref;
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struct nvgpu_mutex lock;
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} profile;
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#endif
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struct nvgpu_mutex userd_mutex;
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struct nvgpu_mem *userd_slabs;
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u32 num_userd_slabs;
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u32 num_channels_per_slab;
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u32 userd_entry_size;
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u64 userd_gpu_va;
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unsigned int used_channels;
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struct nvgpu_channel *channel;
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/* zero-kref'd channels here */
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struct nvgpu_list_node free_chs;
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struct nvgpu_mutex free_chs_mutex;
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struct nvgpu_mutex engines_reset_mutex;
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struct nvgpu_spinlock runlist_submit_lock;
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struct nvgpu_tsg *tsg;
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struct nvgpu_mutex tsg_inuse_mutex;
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void (*remove_support)(struct nvgpu_fifo *f);
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bool sw_ready;
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struct {
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/* share info between isrs and non-isr code */
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struct {
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struct nvgpu_mutex mutex;
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} isr;
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struct {
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u32 device_fatal_0;
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u32 channel_fatal_0;
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u32 restartable_0;
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} pbdma;
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struct {
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} engine;
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} intr;
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unsigned long deferred_fault_engines;
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bool deferred_reset_pending;
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struct nvgpu_mutex deferred_reset_mutex;
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u32 max_subctx_count;
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u32 channel_base;
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};
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int gk20a_init_fifo_reset_enable_hw(struct gk20a *g);
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int gk20a_init_fifo_setup_hw(struct gk20a *g);
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void gk20a_fifo_bar1_snooping_disable(struct gk20a *g);
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int gk20a_fifo_init_pbdma_map(struct gk20a *g, u32 *pbdma_map, u32 num_pbdma);
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u32 gk20a_fifo_get_runlist_timeslice(struct gk20a *g);
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u32 gk20a_fifo_get_pb_timeslice(struct gk20a *g);
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#endif /* FIFO_GK20A_H */
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