Thomas Fleury 3fde3ae650 gpu: nvgpu: move set_timeslice to tsg ...

Moved the following HALs from fifo to tsg
- set_timeslice
- default_timeslice_us

Renamed
- gk20a_tsg_set_timeslice -> nvgpu_tsg_set_timeslice
- min_timeslice_us -> tsg_timeslice_min_us
- max_timeslice_us -> tsg_timeslice_max_us

Scale timeslice to take into account PTIMER clock in
nvgpu_runlist_append_tsg.

Removed gk20a_channel_get_timescale_from_timeslice, and
instead moved timeout and scale computation into runlist HAL,
when building TSG entry:
- runlist.get_tsg_entry

Use ram_rl_entry_* accessors instead of hard coded values
for default and max timeslices.

Added #defines for min, max and default timeslices.

Jira NVGPU-3156

Change-Id: I447266c087c47c89cb6a4a7e4f30acf834b758f0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100052
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-04-26 14:15:49 -07:00

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