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git://nv-tegra.nvidia.com/linux-nvgpu.git
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17c581d755
The basic nvgpu_mem_sgl implementation provides support for OS specific scatter-gather list implementations by simply copying them node by node. This is inefficient, taking extra time and memory. This patch implements an nvgpu_mem_sgt struct to act as a header which is inserted at the front of any scatter- gather list implementation. This labels every struct with a set of ops which can be used to interact with the attached scatter gather list. Since nvgpu common code only has to interact with these function pointers, any sgl implementation can be used. Initialization only requires the allocation of a single struct, removing the need to copy or iterate through the sgl being converted. Jira NVGPU-186 Change-Id: I2994f804a4a4cc141b702e987e9081d8560ba2e8 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1541426 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
133 lines
3.2 KiB
C
133 lines
3.2 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/pramin.h>
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#include <nvgpu/page_allocator.h>
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#include "gk20a/gk20a.h"
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/*
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* Flip this to force all gk20a_mem* accesses via PRAMIN from the start of the
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* boot, even for buffers that would work via cpu_va. In runtime, the flag is
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* in debugfs, called "force_pramin".
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*/
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#define GK20A_FORCE_PRAMIN_DEFAULT false
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void pramin_access_batch_rd_n(struct gk20a *g, u32 start, u32 words, u32 **arg)
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{
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u32 r = start, *dest_u32 = *arg;
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if (!g->regs) {
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__gk20a_warn_on_no_regs();
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return;
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}
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while (words--) {
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*dest_u32++ = gk20a_readl(g, r);
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r += sizeof(u32);
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}
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*arg = dest_u32;
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}
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void pramin_access_batch_wr_n(struct gk20a *g, u32 start, u32 words, u32 **arg)
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{
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u32 r = start, *src_u32 = *arg;
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if (!g->regs) {
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__gk20a_warn_on_no_regs();
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return;
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}
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while (words--) {
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writel_relaxed(*src_u32++, g->regs + r);
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r += sizeof(u32);
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}
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*arg = src_u32;
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}
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void pramin_access_batch_set(struct gk20a *g, u32 start, u32 words, u32 **arg)
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{
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u32 r = start, repeat = **arg;
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if (!g->regs) {
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__gk20a_warn_on_no_regs();
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return;
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}
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while (words--) {
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writel_relaxed(repeat, g->regs + r);
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r += sizeof(u32);
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}
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}
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/*
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* The PRAMIN range is 1 MB, must change base addr if a buffer crosses that.
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* This same loop is used for read/write/memset. Offset and size in bytes.
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* One call to "loop" is done per range, with "arg" supplied.
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*/
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void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem,
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u32 offset, u32 size, pramin_access_batch_fn loop, u32 **arg)
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{
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struct nvgpu_page_alloc *alloc = NULL;
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struct nvgpu_sgt *sgt;
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void *sgl;
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u32 byteoff, start_reg, until_end, n;
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alloc = get_vidmem_page_alloc(mem->priv.sgt->sgl);
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sgt = &alloc->sgt;
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for (sgl = sgt->sgl; sgl; sgl = nvgpu_sgt_get_next(sgt, sgl)) {
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if (offset >= nvgpu_sgt_get_length(sgt, sgl))
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offset -= nvgpu_sgt_get_length(sgt, sgl);
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else
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break;
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}
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while (size) {
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u32 sgl_len = (u32)nvgpu_sgt_get_length(sgt, sgl);
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byteoff = g->ops.pramin.enter(g, mem, sgt, sgl,
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offset / sizeof(u32));
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start_reg = g->ops.pramin.data032_r(byteoff / sizeof(u32));
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until_end = SZ_1M - (byteoff & (SZ_1M - 1));
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n = min3(size, until_end, (u32)(sgl_len - offset));
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loop(g, start_reg, n / sizeof(u32), arg);
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/* read back to synchronize accesses */
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gk20a_readl(g, start_reg);
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g->ops.pramin.exit(g, mem, sgl);
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size -= n;
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if (n == (sgl_len - offset)) {
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sgl = nvgpu_sgt_get_next(sgt, sgl);
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offset = 0;
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} else {
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offset += n;
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}
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}
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}
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void nvgpu_init_pramin(struct mm_gk20a *mm)
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{
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mm->pramin_window = 0;
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nvgpu_spinlock_init(&mm->pramin_window_lock);
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mm->force_pramin = GK20A_FORCE_PRAMIN_DEFAULT;
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}
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