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191aeb5cf8
The exec_regops() API was using a u64 for the num_ops parameter. The lower level APIs used by exec_regops() expect u32s for this value. Update the interface to use u32. This eliminates MISRA Rule 10.3 violations for assignment of objects of different essential or narrower types. JIRA: NVGPU-3023 Change-Id: I5a2a22916f81d8b3d882d224d07eedffcde1e3ee Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2084207 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
93 lines
3.6 KiB
C
93 lines
3.6 KiB
C
/*
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* Tegra GK20A GPU Debugger Driver Register Ops
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*
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* Copyright (c) 2013-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_REGOPS_H
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#define NVGPU_REGOPS_H
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/*
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* Register operations
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* All operations are targeted towards first channel
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* attached to debug session
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*/
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/* valid op values */
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#define NVGPU_DBG_REG_OP_READ_32 0x00000000U
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#define NVGPU_DBG_REG_OP_WRITE_32 0x00000001U
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#define NVGPU_DBG_REG_OP_READ_64 0x00000002U
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#define NVGPU_DBG_REG_OP_WRITE_64 0x00000003U
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/* note: 8b ops are unsupported */
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#define NVGPU_DBG_REG_OP_READ_08 0x00000004U
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#define NVGPU_DBG_REG_OP_WRITE_08 0x00000005U
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/* valid type values */
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#define NVGPU_DBG_REG_OP_TYPE_GLOBAL 0x00000000U
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#define NVGPU_DBG_REG_OP_TYPE_GR_CTX 0x00000001U
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#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_TPC 0x00000002U
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#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_SM 0x00000004U
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#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_CROP 0x00000008U
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#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_ZROP 0x00000010U
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/*#define NVGPU_DBG_REG_OP_TYPE_FB (0x00000020)*/
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#define NVGPU_DBG_REG_OP_TYPE_GR_CTX_QUAD 0x00000040U
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/* valid status values */
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#define NVGPU_DBG_REG_OP_STATUS_SUCCESS 0x00000000U
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#define NVGPU_DBG_REG_OP_STATUS_INVALID_OP 0x00000001U
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#define NVGPU_DBG_REG_OP_STATUS_INVALID_TYPE 0x00000002U
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#define NVGPU_DBG_REG_OP_STATUS_INVALID_OFFSET 0x00000004U
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#define NVGPU_DBG_REG_OP_STATUS_UNSUPPORTED_OP 0x00000008U
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#define NVGPU_DBG_REG_OP_STATUS_INVALID_MASK 0x00000010U
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struct nvgpu_dbg_reg_op {
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u8 op;
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u8 type;
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u8 status;
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u8 quad;
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u32 group_mask;
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u32 sub_group_mask;
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u32 offset;
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u32 value_lo;
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u32 value_hi;
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u32 and_n_mask_lo;
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u32 and_n_mask_hi;
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};
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struct regop_offset_range {
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u32 base:24;
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u32 count:8;
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};
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int exec_regops_gk20a(struct gk20a *g,
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struct channel_gk20a *ch,
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struct nvgpu_dbg_reg_op *ops,
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u32 num_ops,
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bool is_profiler,
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bool *is_current_ctx);
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/* turn seriously unwieldy names -> something shorter */
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#define REGOP(x) NVGPU_DBG_REG_OP_##x
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bool reg_op_is_gr_ctx(u8 type);
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bool reg_op_is_read(u8 op);
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bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset);
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#endif /* NVGPU_REGOPS_H */
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