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1933eb7d18
Disabling / enabling of PFIFO must stay inside the isr. It cannot be held disabled outside the isr -- this causes any kind of preemption mechanism to fail in the presence of an MMU fault until the channel resets the engine. Bug 1791696 Change-Id: I16600a8571f6555262a75deb305c1d67eb29581a Signed-off-by: Cory Perry <cperry@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1191026 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>