Philip Elcan 1d1acaaa5e gpu: nvgpu: posix: update align macros for CERT-C ...

The ALIGN() and ALIGN_MASK() macros were causing INT30 CERT-C
violations because of possible wrap issues. Update the macros to check
for potential wrap cases.

JIRA NVGPU-3515

Change-Id: I2af50fe036e8fcaf27e484af134c4a54fa4d19a1
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124998
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-05-24 13:35:35 -07:00

..

nvgpu

gpu: nvgpu: posix: update align macros for CERT-C

2019-05-24 13:35:35 -07:00

Makefile

nvgpu: use kernel overlay features

2017-10-29 11:00:55 -07:00