Philip Elcan c6e784a2d9 gpu: nvgpu: priv_ring: reduce CCM for gp10b_priv_ring_isr ...

Reduce the code complexity of gp10b_priv_ring_isr() by making helper
functions gp10b_priv_ring_isr_handle_status0() and
gp10b_priv_ring_isr_handle_status0().

This reduces the TCC metric from 14 to 4.

JIRA NVGPU-4064

Change-Id: I87537d37b2335fe0ce7c103e2d7851b0992eaff1
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2212888
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2020-12-15 14:05:52 -06:00

..

priv_ring_gm20b_fusa.c

gpu: nvgpu: init: add return for all init APIs

2020-12-15 14:05:52 -06:00

priv_ring_gm20b.c

gpu: nvgpu: move safe code HAL files to fusa

2019-07-03 02:46:15 -07:00

priv_ring_gm20b.h

gpu: nvgpu: init: add return for all init APIs

2020-12-15 14:05:52 -06:00

priv_ring_gp10b_fusa.c

gpu: nvgpu: priv_ring: reduce CCM for gp10b_priv_ring_isr

2020-12-15 14:05:52 -06:00

priv_ring_gp10b.h

gpu: nvgpu: move chip specific priv_ring to hal

2019-02-27 13:43:47 -08:00