mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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0e873d6348
Added new hal in top unit to get number of ltcs and used this hal in ltc unit. With this one hardware header dependency hw_top_gxxxx.h from ltc unit is removed. Also used priv_ring unit hal enum_ltc to avoid dependency on hw_pri_ringmaster_gxxxx.h. JIRA NVGPU-3445 Change-Id: I5b6a2d87ecc663ce5b9fb85ff1e1fe97d7eb6d9a Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2170400 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
131 lines
3.6 KiB
C
131 lines
3.6 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/top.h>
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#include <nvgpu/types.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "top_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_top_gm20b.h>
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int gm20b_device_info_parse_enum(struct gk20a *g, u32 table_entry,
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u32 *engine_id, u32 *runlist_id,
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u32 *intr_id, u32 *reset_id)
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{
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if (top_device_info_entry_v(table_entry) !=
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top_device_info_entry_enum_v()) {
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nvgpu_err(g, "Invalid device_info_enum %u",
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top_device_info_entry_v(table_entry));
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return -EINVAL;
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}
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nvgpu_log_info(g, "Entry_enum to be parsed 0x%x", table_entry);
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if (top_device_info_engine_v(table_entry) ==
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top_device_info_engine_valid_v()) {
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*engine_id = top_device_info_engine_enum_v(table_entry);
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} else {
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*engine_id = U32_MAX;
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}
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nvgpu_log_info(g, "Engine_id: %u", *engine_id);
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if (top_device_info_runlist_v(table_entry) ==
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top_device_info_runlist_valid_v()) {
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*runlist_id = top_device_info_runlist_enum_v(table_entry);
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} else {
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*runlist_id = U32_MAX;
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}
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nvgpu_log_info(g, "Runlist_id: %u", *runlist_id);
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if (top_device_info_intr_v(table_entry) ==
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top_device_info_intr_valid_v()) {
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*intr_id = top_device_info_intr_enum_v(table_entry);
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} else {
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*intr_id = U32_MAX;
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}
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nvgpu_log_info(g, "Intr_id: %u", *intr_id);
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if (top_device_info_reset_v(table_entry) ==
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top_device_info_reset_valid_v()) {
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*reset_id = top_device_info_reset_enum_v(table_entry);
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} else {
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*reset_id = U32_MAX;
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}
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nvgpu_log_info(g, "Reset_id: %u", *reset_id);
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return 0;
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}
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bool gm20b_is_engine_gr(struct gk20a *g, u32 engine_type)
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{
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return (engine_type == top_device_info_type_enum_graphics_v());
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}
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u32 gm20b_top_get_max_gpc_count(struct gk20a *g)
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{
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u32 tmp;
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tmp = nvgpu_readl(g, top_num_gpcs_r());
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return top_num_gpcs_value_v(tmp);
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}
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u32 gm20b_top_get_max_tpc_per_gpc_count(struct gk20a *g)
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{
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u32 tmp;
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tmp = nvgpu_readl(g, top_tpc_per_gpc_r());
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return top_tpc_per_gpc_value_v(tmp);
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}
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u32 gm20b_top_get_max_fbps_count(struct gk20a *g)
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{
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u32 tmp;
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tmp = nvgpu_readl(g, top_num_fbps_r());
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return top_num_fbps_value_v(tmp);
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}
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u32 gm20b_top_get_max_ltc_per_fbp(struct gk20a *g)
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{
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u32 tmp;
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tmp = nvgpu_readl(g, top_ltc_per_fbp_r());
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return top_ltc_per_fbp_value_v(tmp);
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}
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u32 gm20b_top_get_max_lts_per_ltc(struct gk20a *g)
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{
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u32 tmp;
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tmp = nvgpu_readl(g, top_slices_per_ltc_r());
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return top_slices_per_ltc_value_v(tmp);
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}
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u32 gm20b_top_get_num_ltcs(struct gk20a *g)
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{
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u32 tmp;
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tmp = nvgpu_readl(g, top_num_ltcs_r());
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return top_num_ltcs_value_v(tmp);
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}
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