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git://nv-tegra.nvidia.com/linux-nvgpu.git
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25abe6a352
This is added to compile out some non safety code from safety build. JIRA NVGPU-4146 Change-Id: Ie2b05f7c1bf1d0400184ae95d39103828c28de1e Signed-off-by: dinesh <dt@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2217415 Reviewed-by: Philip Elcan <pelcan@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
133 lines
2.8 KiB
C
133 lines
2.8 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/nvhost.h>
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int nvgpu_get_nvhost_dev(struct gk20a *g)
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{
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BUG();
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return 0;
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}
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void nvgpu_free_nvhost_dev(struct gk20a *g)
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{
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BUG();
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}
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bool nvgpu_nvhost_syncpt_is_valid_pt_ext(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
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{
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BUG();
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return false;
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}
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void nvgpu_nvhost_syncpt_set_min_eq_max_ext(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
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{
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BUG();
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}
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void nvgpu_nvhost_syncpt_put_ref_ext(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
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{
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BUG();
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}
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u32 nvgpu_nvhost_get_syncpt_client_managed(
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struct nvgpu_nvhost_dev *nvhost_dev,
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const char *syncpt_name)
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{
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BUG();
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return 0U;
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}
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u32 nvgpu_nvhost_syncpt_read_maxval(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
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{
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BUG();
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return 0U;
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}
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void nvgpu_nvhost_syncpt_set_safe_state(
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struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
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{
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BUG();
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}
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#ifdef CONFIG_SYNC
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u32 nvgpu_nvhost_sync_pt_id(struct sync_pt *pt)
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{
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BUG();
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return 0U;
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}
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u32 nvgpu_nvhost_sync_pt_thresh(struct sync_pt *pt)
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{
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BUG();
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return 0U;
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}
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struct sync_fence *nvgpu_nvhost_sync_fdget(int fd)
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{
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BUG();
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return NULL;
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}
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int nvgpu_nvhost_sync_num_pts(struct sync_fence *fence)
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{
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BUG();
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return 0;
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}
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struct sync_fence *nvgpu_nvhost_sync_create_fence(
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struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 thresh, const char *name)
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{
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BUG();
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return NULL;
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}
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#endif /* CONFIG_SYNC */
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#ifdef CONFIG_TEGRA_T19X_GRHOST
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int nvgpu_nvhost_syncpt_unit_interface_get_aperture(
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struct nvgpu_nvhost_dev *nvhost_dev,
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u64 *base, size_t *size)
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{
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BUG();
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return 0;
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}
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u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id)
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{
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BUG();
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return 0U;
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}
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int nvgpu_nvhost_syncpt_init(struct gk20a *g)
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{
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return -ENOSYS;
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}
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#endif
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