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13cc7ea93d
once gpu is powered off i.e. power_on set to false, nvgpu isr does not handle stall/nonstall irq. Depending upon state of gpu, this can result in either of following errors: 1) irq 458: nobody cared (try booting with the "irqpoll" option) 2) "HSM ERROR 42, GPU" from SCE if it detects that an interrupt is not in time. Fix these by masking all interrupts just before gpu power off as nvgpu won't be handling any irq anymore. While masking interrupts, if there are any pending interrupts, then report those with a log message. Bug 1987855 Bug 200424832 Change-Id: I95b087f5c24d439e5da26c6e4fff74d8a525f291 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770802 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
49 lines
2.2 KiB
C
49 lines
2.2 KiB
C
/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef MC_GK20A_H
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#define MC_GK20A_H
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struct gk20a;
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void mc_gk20a_intr_mask(struct gk20a *g);
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void mc_gk20a_intr_enable(struct gk20a *g);
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void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable,
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bool is_stalling, u32 mask);
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void mc_gk20a_isr_stall(struct gk20a *g);
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u32 mc_gk20a_intr_stall(struct gk20a *g);
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void mc_gk20a_intr_stall_pause(struct gk20a *g);
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void mc_gk20a_intr_stall_resume(struct gk20a *g);
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u32 mc_gk20a_intr_nonstall(struct gk20a *g);
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u32 mc_gk20a_isr_nonstall(struct gk20a *g);
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void mc_gk20a_intr_nonstall_pause(struct gk20a *g);
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void mc_gk20a_intr_nonstall_resume(struct gk20a *g);
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void gk20a_mc_enable(struct gk20a *g, u32 units);
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void gk20a_mc_disable(struct gk20a *g, u32 units);
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void gk20a_mc_reset(struct gk20a *g, u32 units);
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u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
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bool mc_gk20a_is_intr1_pending(struct gk20a *g,
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enum nvgpu_unit unit, u32 mc_intr_1);
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void mc_gk20a_log_pending_intrs(struct gk20a *g);
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void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops);
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#endif /* MC_GK20A_H */
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