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503d489dba
- For Mode-E ctxsw it is required that engine_sel is set to 0xFFFFFFFF. - Default 0 is a valid signal and causes problems. Bug 2106999 Change-Id: I5cdb4441a8e6d7e8133c31a9e361b54611dd2995 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770755 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
53 lines
2.2 KiB
C
53 lines
2.2 KiB
C
/*
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* GV100 GPU GR
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*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _NVGPU_GR_GV100_H_
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#define _NVGPU_GR_GV100_H_
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void gr_gv100_bundle_cb_defaults(struct gk20a *g);
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void gr_gv100_cb_size_default(struct gk20a *g);
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void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
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int gr_gv100_init_sm_id_table(struct gk20a *g);
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void gr_gv100_program_sm_id_numbering(struct gk20a *g,
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u32 gpc, u32 tpc, u32 smid);
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int gr_gv100_load_smid_config(struct gk20a *g);
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u32 gr_gv100_get_patch_slots(struct gk20a *g);
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int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g,
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struct ctxsw_buf_offset_map_entry *map,
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struct aiv_list_gk20a *regs,
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u32 *count, u32 *offset,
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u32 max_cnt, u32 base,
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u32 num_fbpas, u32 stride, u32 mask);
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int gr_gv100_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map,
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struct aiv_list_gk20a *regs,
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u32 *count, u32 *offset,
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u32 max_cnt, u32 base, u32 mask);
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void gr_gv100_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr,
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u32 num_fbpas,
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u32 *priv_addr_table, u32 *t);
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void gr_gv100_init_gpc_mmu(struct gk20a *g);
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u32 gr_gv100_get_hw_accessor_stream_out_mode(void);
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void gr_gv100_init_hwpm_pmm_register(struct gk20a *g);
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#endif
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