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e14fdcd8f1
- Write new pm mode to context buffer header. Ucode use this mode to enable mode-e context switch. This is Mode-B context switch of PMs with Mode-E streamout on one context. If this mode is set, Ucode makes sure that Mode-E pipe (perfmons, routers, pma) is idle before it context switches PMs. - This allows us to collect counters in a secure way (i.e. on context basis) with stream out. Bug 2106999 Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1760366 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
75 lines
3.1 KiB
C
75 lines
3.1 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _GR_VGPU_H_
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#define _GR_VGPU_H_
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#include <nvgpu/types.h>
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struct gk20a;
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struct channel_gk20a;
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struct gr_gk20a;
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struct gr_zcull_info;
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struct zbc_entry;
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struct zbc_query_params;
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struct dbg_session_gk20a;
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struct tsg_gk20a;
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void vgpu_gr_detect_sm_arch(struct gk20a *g);
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void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg);
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void vgpu_gr_free_tsg_ctx(struct tsg_gk20a *tsg);
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int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags);
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int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
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struct channel_gk20a *c, u64 zcull_va,
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u32 mode);
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int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
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struct gr_zcull_info *zcull_params);
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u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
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u32 vgpu_gr_get_max_fbps_count(struct gk20a *g);
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u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g);
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u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g);
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u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g);
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u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g);
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int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_entry *zbc_val);
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int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
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struct zbc_query_params *query_params);
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int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
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struct channel_gk20a *ch, u64 sms, bool enable);
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int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
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struct channel_gk20a *ch, bool enable);
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int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
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struct channel_gk20a *ch, u64 gpu_va, u32 mode);
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int vgpu_gr_clear_sm_error_state(struct gk20a *g,
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struct channel_gk20a *ch, u32 sm_id);
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int vgpu_gr_suspend_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int vgpu_gr_resume_contexts(struct gk20a *g,
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struct dbg_session_gk20a *dbg_s,
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int *ctx_resident_ch_fd);
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int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
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int vgpu_gr_init_sm_id_table(struct gk20a *g);
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int vgpu_gr_init_fs_state(struct gk20a *g);
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int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable);
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#endif
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