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1c13da1d29
Changed the enum gmmu_pgsz_gk20a into macros and changed all the instances of it. The enum gmmu_pgsz_gk20a was being used in for loops, where it was compared with an integer. This violates MISRA rule 10.4, which only allows arithmetic operations on operands of the same essential type category. Changing this enum into macro will fix this violation. JIRA NVGPU-993 Change-Id: I6f18b08bc7548093d99e8229378415bcdec749e3 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795593 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
49 lines
1.9 KiB
C
49 lines
1.9 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _MM_VGPU_H_
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#define _MM_VGPU_H_
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struct nvgpu_mem;
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struct channel_gk20a;
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struct vm_gk20a_mapping_batch;
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struct gk20a_as_share;
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struct vm_gk20a;
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enum gk20a_mem_rw_flag;
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void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm,
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u64 vaddr,
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u64 size,
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u32 pgsz_idx,
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bool va_allocated,
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enum gk20a_mem_rw_flag rw_flag,
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bool sparse,
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struct vm_gk20a_mapping_batch *batch);
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int vgpu_vm_bind_channel(struct vm_gk20a *vm,
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struct channel_gk20a *ch);
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int vgpu_mm_fb_flush(struct gk20a *g);
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void vgpu_mm_l2_invalidate(struct gk20a *g);
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void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate);
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void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
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void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable);
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#endif
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