mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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2ad015f7a5
Currently, nvgpu_writel_loop() writes to a register and immediately checks if register value is updated. It might take some time for hardware registers to get updated with value written by software. Modify nvgpu_writel_loop() to accept number of retries to check if register value is updated and assert with nvgpu_assert(). Also, move nvgpu_writel_loop() to common code and use generic nvgpu_readl() and nvgpu_writel() APIs. JIRA NVGPU-5490 Change-Id: Iaaf24203a91eee3d05de7d0c7dea18113367de5f Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2348628 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
121 lines
2.8 KiB
C
121 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_init.h>
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#include "os_linux.h"
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static void nvgpu_warn_on_no_regs(void)
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{
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WARN_ONCE(true, "Attempted access to GPU regs after unmapping!");
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}
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void nvgpu_writel(struct gk20a *g, u32 r, u32 v)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->regs)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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writel_relaxed(v, l->regs + r);
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nvgpu_wmb();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
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}
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}
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void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->regs)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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writel_relaxed(v, l->regs + r);
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}
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}
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u32 nvgpu_readl(struct gk20a *g, u32 r)
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{
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u32 v = nvgpu_readl_impl(g, r);
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if (v == 0xffffffff)
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nvgpu_check_gpu_state(g);
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return v;
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}
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u32 nvgpu_readl_impl(struct gk20a *g, u32 r)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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u32 v = 0xffffffff;
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if (unlikely(!l->regs)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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v = readl(l->regs + r);
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
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}
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return v;
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}
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void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->bar1)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
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} else {
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nvgpu_wmb();
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writel_relaxed(v, l->bar1 + b);
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x", b, v);
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}
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}
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u32 nvgpu_bar1_readl(struct gk20a *g, u32 b)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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u32 v = 0xffffffff;
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if (unlikely(!l->bar1)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
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} else {
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v = readl(l->bar1 + b);
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x", b, v);
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}
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return v;
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}
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bool nvgpu_io_exists(struct gk20a *g)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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return l->regs != NULL;
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}
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bool nvgpu_io_valid_reg(struct gk20a *g, u32 r)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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return r < resource_size(l->regs);
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}
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