mirror of
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673dd97160
- Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/" - Included header file "pmu.h" to dependent file & removed "pmu_gk20a.h" include if its usage is not present. - Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent source & header files. JIRA NVGPU-56 Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1479209 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
194 lines
6.7 KiB
C
194 lines
6.7 KiB
C
/*
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* drivers/video/tegra/host/gk20a/pmu_gk20a.h
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*
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* GK20A PMU (aka. gPMU outside gk20a context)
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*
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* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __PMU_GK20A_H__
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#define __PMU_GK20A_H__
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#include <linux/version.h>
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#include <nvgpu/flcnif_cmn.h>
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include <nvgpu/pmu.h>
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struct nvgpu_firmware;
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#define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe)
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#define APP_VERSION_NC_3 21688026
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#define APP_VERSION_NC_2 20429989
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#define APP_VERSION_NC_1 20313802
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#define APP_VERSION_NC_0 20360931
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#define APP_VERSION_GM206 20652057
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#define APP_VERSION_NV_GPU 21307569
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#define APP_VERSION_NV_GPU_1 21308030
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#define APP_VERSION_GM20B_5 20490253
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#define APP_VERSION_GM20B_4 19008461
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#define APP_VERSION_GM20B_3 18935575
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#define APP_VERSION_GM20B_2 18694072
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#define APP_VERSION_GM20B_1 18547257
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#define APP_VERSION_GM20B 17615280
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#define APP_VERSION_3 18357968
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#define APP_VERSION_2 18542378
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#define APP_VERSION_1 17997577 /*Obsolete this once 18357968 gets in*/
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#define APP_VERSION_0 16856675
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/*Fuse defines*/
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
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#define FUSE_GCPLEX_CONFIG_FUSE_0 0x2C8
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#endif
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#define PMU_PGENG_GR_BUFFER_IDX_INIT (0)
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#define PMU_PGENG_GR_BUFFER_IDX_ZBC (1)
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#define PMU_PGENG_GR_BUFFER_IDX_FECS (2)
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struct pmu_payload {
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struct {
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void *buf;
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u32 offset;
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u32 size;
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u32 fb_size;
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} in, out;
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};
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struct pmu_surface {
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struct nvgpu_mem vidmem_desc;
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struct nvgpu_mem sysmem_desc;
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struct flcn_mem_desc_v0 params;
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};
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/*PG defines used by nvpgu-pmu*/
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struct pmu_pg_stats_data {
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u32 gating_cnt;
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u32 ingating_time;
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u32 ungating_time;
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u32 avg_entry_latency_us;
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u32 avg_exit_latency_us;
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};
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#define PMU_PG_IDLE_THRESHOLD_SIM 1000
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#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM 4000000
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/* TBD: QT or else ? */
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#define PMU_PG_IDLE_THRESHOLD 15000
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#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD 1000000
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#define PMU_PG_LPWR_FEATURE_RPPG 0x0
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#define PMU_PG_LPWR_FEATURE_MSCG 0x1
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/* state transition :
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OFF => [OFF_ON_PENDING optional] => ON_PENDING => ON => OFF
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ON => OFF is always synchronized */
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#define PMU_ELPG_STAT_OFF 0 /* elpg is off */
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#define PMU_ELPG_STAT_ON 1 /* elpg is on */
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#define PMU_ELPG_STAT_ON_PENDING 2 /* elpg is off, ALLOW cmd has been sent, wait for ack */
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#define PMU_ELPG_STAT_OFF_PENDING 3 /* elpg is on, DISALLOW cmd has been sent, wait for ack */
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#define PMU_ELPG_STAT_OFF_ON_PENDING 4 /* elpg is off, caller has requested on, but ALLOW
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cmd hasn't been sent due to ENABLE_ALLOW delay */
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#define PG_REQUEST_TYPE_GLOBAL 0x0
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#define PG_REQUEST_TYPE_PSTATE 0x1
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#define PMU_MSCG_DISABLED 0
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#define PMU_MSCG_ENABLED 1
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/* Default Sampling Period of AELPG */
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#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000)
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/* Default values of APCTRL parameters */
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#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100)
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#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000)
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#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000)
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#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
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/*PG defines used by nvpgu-pmu*/
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int gk20a_init_pmu_support(struct gk20a *g);
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int gk20a_init_pmu_bind_fecs(struct gk20a *g);
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void gk20a_pmu_isr(struct gk20a *g);
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/* send a cmd to pmu */
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int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, struct pmu_msg *msg,
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struct pmu_payload *payload, u32 queue_id,
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pmu_callback callback, void* cb_param,
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u32 *seq_desc, unsigned long timeout);
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int gk20a_pmu_enable_elpg(struct gk20a *g);
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int gk20a_pmu_disable_elpg(struct gk20a *g);
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int gk20a_pmu_pg_global_enable(struct gk20a *g, u32 enable_pg);
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u32 gk20a_pmu_pg_engines_list(struct gk20a *g);
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u32 gk20a_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id);
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void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
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int gk20a_pmu_perfmon_enable(struct gk20a *g, bool enable);
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int pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token);
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int pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
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int gk20a_pmu_destroy(struct gk20a *g);
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int gk20a_pmu_load_norm(struct gk20a *g, u32 *load);
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int gk20a_pmu_load_update(struct gk20a *g);
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void gk20a_pmu_reset_load_counters(struct gk20a *g);
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void gk20a_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles,
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u32 *total_cycles);
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void gk20a_init_pmu_ops(struct gpu_ops *gops);
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void pmu_copy_to_dmem(struct nvgpu_pmu *pmu,
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u32 dst, u8 *src, u32 size, u8 port);
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void pmu_copy_from_dmem(struct nvgpu_pmu *pmu,
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u32 src, u8 *dst, u32 size, u8 port);
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int pmu_reset(struct nvgpu_pmu *pmu);
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int pmu_bootstrap(struct nvgpu_pmu *pmu);
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int gk20a_init_pmu(struct nvgpu_pmu *pmu);
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void pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
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void gk20a_remove_pmu_support(struct nvgpu_pmu *pmu);
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void pmu_seq_init(struct nvgpu_pmu *pmu);
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int gk20a_init_pmu(struct nvgpu_pmu *pmu);
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int gk20a_pmu_ap_send_command(struct gk20a *g,
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union pmu_ap_cmd *p_ap_cmd, bool b_block);
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int gk20a_aelpg_init(struct gk20a *g);
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int gk20a_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id);
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void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
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int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms,
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u32 *var, u32 val);
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void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
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void *param, u32 handle, u32 status);
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void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
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struct pmu_pg_stats_data *pg_stat_data);
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int gk20a_pmu_reset(struct gk20a *g);
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int pmu_idle(struct nvgpu_pmu *pmu);
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int pmu_enable_hw(struct nvgpu_pmu *pmu, bool enable);
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void gk20a_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem);
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void gk20a_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem,
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struct flcn_mem_desc_v0 *fb);
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int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
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u32 size);
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int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
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u32 size);
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int gk20a_pmu_get_pg_stats(struct gk20a *g,
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u32 pg_engine_id, struct pmu_pg_stats_data *pg_stat_data);
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bool nvgpu_find_hex_in_string(char *strings, struct gk20a *g, u32 *hex_pos);
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int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu);
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int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu);
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#endif /*__PMU_GK20A_H__*/
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