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MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Ifb8cb992a5cb9b04440f162918a8ed2ae17ec928 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822587 GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
78 lines
3.1 KiB
C
78 lines
3.1 KiB
C
/*
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* drivers/video/tegra/host/gk20a/pmu_gk20a.h
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*
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* GK20A PMU (aka. gPMU outside gk20a context)
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*
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* Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GK20A_PMU_GK20A_H
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#define NVGPU_GK20A_PMU_GK20A_H
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#include <nvgpu/flcnif_cmn.h>
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include <nvgpu/pmu.h>
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struct nvgpu_firmware;
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#define ZBC_MASK(i) U16(~(~(0U) << ((i)+1U)) & 0xfffeU)
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bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu);
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void gk20a_pmu_isr(struct gk20a *g);
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u32 gk20a_pmu_pg_engines_list(struct gk20a *g);
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u32 gk20a_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id);
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void gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
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void gk20a_pmu_init_perfmon_counter(struct gk20a *g);
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void gk20a_pmu_pg_idle_counter_config(struct gk20a *g, u32 pg_engine_id);
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int gk20a_pmu_mutex_acquire(struct nvgpu_pmu *pmu, u32 id, u32 *token);
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int gk20a_pmu_mutex_release(struct nvgpu_pmu *pmu, u32 id, u32 *token);
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int gk20a_pmu_queue_head(struct gk20a *g, struct nvgpu_falcon_queue *queue,
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u32 *head, bool set);
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int gk20a_pmu_queue_tail(struct gk20a *g, struct nvgpu_falcon_queue *queue,
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u32 *tail, bool set);
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void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set);
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u32 gk20a_pmu_read_idle_counter(struct gk20a *g, u32 counter_id);
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void gk20a_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id);
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void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr);
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bool gk20a_is_pmu_supported(struct gk20a *g);
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int pmu_bootstrap(struct nvgpu_pmu *pmu);
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void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu);
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void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);
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void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
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void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
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void *param, u32 handle, u32 status);
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void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
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struct pmu_pg_stats_data *pg_stat_data);
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bool gk20a_pmu_is_engine_in_reset(struct gk20a *g);
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int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset);
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u32 gk20a_pmu_get_irqdest(struct gk20a *g);
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#endif /*NVGPU_GK20A_PMU_GK20A_H*/
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