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2d14c3a619b0e13147550e022739a5df574f8d30
Turing board (PG189) variants (A00, A01, A02, A03) need different dealys for valid power good (PG) signal. To support all board variants change the delay to minimum required value of 250ms. Bug 200452556 JIRA NVGPU-1100 Change-Id: Iba2a6b17dec7552197cb0b7873132d83e9e09aea Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1987659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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