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66ec347db4
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43d94067a1d7eafba4cdb28311e0ce25812013a7 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522553 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
30 lines
986 B
C
30 lines
986 B
C
/*
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* GM20B Fifo
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _NVHOST_GM20B_FIFO
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#define _NVHOST_GM20B_FIFO
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struct gk20a;
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void channel_gm20b_bind(struct channel_gk20a *c);
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void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
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unsigned long engine_ids);
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u32 gm20b_fifo_get_num_fifos(struct gk20a *g);
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void gm20b_device_info_data_parse(struct gk20a *g,
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u32 table_entry, u32 *inst_id,
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u32 *pri_base, u32 *fault_id);
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void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
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#endif
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