mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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34b34915f8
MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch changes calls to nvgpu_falcon_bootstrap to handle error codes. JIRA NVGPU-677 Change-Id: I1d9df6053c727e7eb3d99682ff7bb06267608a54 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2008797 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
311 lines
8.4 KiB
C
311 lines
8.4 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/mutex.h>
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#ifdef CONFIG_TEGRA_NVLINK
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#include <nvlink/common/tegra-nvlink.h>
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#endif
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvlink.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/firmware.h>
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#ifdef CONFIG_TEGRA_NVLINK
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int nvgpu_nvlink_enumerate(struct gk20a *g)
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{
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struct nvlink_device *ndev = (struct nvlink_device *) g->nvlink.priv;
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if (!ndev)
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return -ENODEV;
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return nvlink_enumerate(ndev);
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}
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int nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off)
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{
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struct nvlink_device *ndev = (struct nvlink_device *) g->nvlink.priv;
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if (!ndev)
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return -ENODEV;
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/* Check if the link is connected */
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if (!g->nvlink.links[link_id].remote_info.is_connected)
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return -ENODEV;
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if (from_off)
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return nvlink_transition_intranode_conn_off_to_safe(ndev);
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return nvlink_train_intranode_conn_safe_to_hs(ndev);
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}
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void nvgpu_nvlink_free_minion_used_mem(struct gk20a *g,
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struct nvgpu_firmware *nvgpu_minion_fw)
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{
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struct nvlink_device *ndev = (struct nvlink_device *) g->nvlink.priv;
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struct minion_hdr *minion_hdr = &ndev->minion_hdr;
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nvgpu_kfree(g, minion_hdr->app_code_offsets);
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nvgpu_kfree(g, minion_hdr->app_code_sizes);
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nvgpu_kfree(g, minion_hdr->app_data_offsets);
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nvgpu_kfree(g, minion_hdr->app_data_sizes);
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if (nvgpu_minion_fw) {
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nvgpu_release_firmware(g, nvgpu_minion_fw);
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ndev->minion_img = NULL;
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}
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}
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/*
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* Load minion FW
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*/
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int nvgpu_nvlink_minion_load_ucode(struct gk20a *g,
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struct nvgpu_firmware *nvgpu_minion_fw)
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{
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int err = 0;
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struct nvlink_device *ndev = (struct nvlink_device *) g->nvlink.priv;
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struct minion_hdr *minion_hdr = &ndev->minion_hdr;
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u32 data_idx = 0;
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u32 app = 0;
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nvgpu_log_fn(g, " ");
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/* Read ucode header */
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minion_hdr->os_code_offset = nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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minion_hdr->os_code_size = nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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minion_hdr->os_data_offset = nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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minion_hdr->os_data_size = nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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minion_hdr->num_apps = nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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nvgpu_log(g, gpu_dbg_nvlink,
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"MINION Ucode Header Info:");
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nvgpu_log(g, gpu_dbg_nvlink,
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"-------------------------");
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nvgpu_log(g, gpu_dbg_nvlink,
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" - OS Code Offset = %u", minion_hdr->os_code_offset);
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nvgpu_log(g, gpu_dbg_nvlink,
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" - OS Code Size = %u", minion_hdr->os_code_size);
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nvgpu_log(g, gpu_dbg_nvlink,
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" - OS Data Offset = %u", minion_hdr->os_data_offset);
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nvgpu_log(g, gpu_dbg_nvlink,
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" - OS Data Size = %u", minion_hdr->os_data_size);
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nvgpu_log(g, gpu_dbg_nvlink,
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" - Num Apps = %u", minion_hdr->num_apps);
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/* Allocate offset/size arrays for all the ucode apps */
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minion_hdr->app_code_offsets = nvgpu_kcalloc(g,
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minion_hdr->num_apps,
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sizeof(u32));
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if (!minion_hdr->app_code_offsets) {
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nvgpu_err(g, "Couldn't allocate MINION app_code_offsets array");
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return -ENOMEM;
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}
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minion_hdr->app_code_sizes = nvgpu_kcalloc(g,
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minion_hdr->num_apps,
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sizeof(u32));
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if (!minion_hdr->app_code_sizes) {
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nvgpu_err(g, "Couldn't allocate MINION app_code_sizes array");
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return -ENOMEM;
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}
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minion_hdr->app_data_offsets = nvgpu_kcalloc(g,
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minion_hdr->num_apps,
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sizeof(u32));
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if (!minion_hdr->app_data_offsets) {
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nvgpu_err(g, "Couldn't allocate MINION app_data_offsets array");
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return -ENOMEM;
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}
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minion_hdr->app_data_sizes = nvgpu_kcalloc(g,
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minion_hdr->num_apps,
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sizeof(u32));
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if (!minion_hdr->app_data_sizes) {
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nvgpu_err(g, "Couldn't allocate MINION app_data_sizes array");
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return -ENOMEM;
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}
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/* Get app code offsets and sizes */
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for (app = 0; app < minion_hdr->num_apps; app++) {
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minion_hdr->app_code_offsets[app] =
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nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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minion_hdr->app_code_sizes[app] =
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nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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nvgpu_log(g, gpu_dbg_nvlink,
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" - App Code:");
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nvgpu_log(g, gpu_dbg_nvlink,
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" - App #%d: Code Offset = %u, Code Size = %u",
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app,
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minion_hdr->app_code_offsets[app],
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minion_hdr->app_code_sizes[app]);
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}
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/* Get app data offsets and sizes */
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for (app = 0; app < minion_hdr->num_apps; app++) {
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minion_hdr->app_data_offsets[app] =
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nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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minion_hdr->app_data_sizes[app] =
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nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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nvgpu_log(g, gpu_dbg_nvlink,
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" - App Data:");
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nvgpu_log(g, gpu_dbg_nvlink,
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" - App #%d: Data Offset = %u, Data Size = %u",
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app,
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minion_hdr->app_data_offsets[app],
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minion_hdr->app_data_sizes[app]);
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}
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minion_hdr->ovl_offset = nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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minion_hdr->ovl_size = nvgpu_nvlink_minion_extract_word(
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nvgpu_minion_fw,
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data_idx);
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data_idx += 4;
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ndev->minion_img = &(nvgpu_minion_fw->data[data_idx]);
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minion_hdr->ucode_data_size = nvgpu_minion_fw->size - data_idx;
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nvgpu_log(g, gpu_dbg_nvlink,
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" - Overlay Offset = %u", minion_hdr->ovl_offset);
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nvgpu_log(g, gpu_dbg_nvlink,
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" - Overlay Size = %u", minion_hdr->ovl_size);
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nvgpu_log(g, gpu_dbg_nvlink,
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" - Ucode Data Size = %u", minion_hdr->ucode_data_size);
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/* Copy Non Secure IMEM code */
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nvgpu_falcon_copy_to_imem(g->minion_flcn, 0,
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(u8 *)&ndev->minion_img[minion_hdr->os_code_offset],
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minion_hdr->os_code_size, 0, false,
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GET_IMEM_TAG(minion_hdr->os_code_offset));
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/* Copy Non Secure DMEM code */
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nvgpu_falcon_copy_to_dmem(g->minion_flcn, 0,
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(u8 *)&ndev->minion_img[minion_hdr->os_data_offset],
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minion_hdr->os_data_size, 0);
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/* Load the apps securely */
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for (app = 0; app < minion_hdr->num_apps; app++) {
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u32 app_code_start = minion_hdr->app_code_offsets[app];
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u32 app_code_size = minion_hdr->app_code_sizes[app];
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u32 app_data_start = minion_hdr->app_data_offsets[app];
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u32 app_data_size = minion_hdr->app_data_sizes[app];
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if (app_code_size)
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nvgpu_falcon_copy_to_imem(g->minion_flcn,
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app_code_start,
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(u8 *)&ndev->minion_img[app_code_start],
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app_code_size, 0, true,
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GET_IMEM_TAG(app_code_start));
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if (app_data_size)
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nvgpu_falcon_copy_to_dmem(g->minion_flcn,
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app_data_start,
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(u8 *)&ndev->minion_img[app_data_start],
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app_data_size, 0);
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}
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return err;
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}
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#endif /* CONFIG_TEGRA_NVLINK */
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void nvgpu_mss_nvlink_init_credits(struct gk20a *g)
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{
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/* MSS_NVLINK_1_BASE */
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void __iomem *soc1 = ioremap(0x01f20010, 4096);
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/* MSS_NVLINK_2_BASE */
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void __iomem *soc2 = ioremap(0x01f40010, 4096);
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/* MSS_NVLINK_3_BASE */
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void __iomem *soc3 = ioremap(0x01f60010, 4096);
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/* MSS_NVLINK_4_BASE */
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void __iomem *soc4 = ioremap(0x01f80010, 4096);
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u32 val;
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nvgpu_log(g, gpu_dbg_info, "init nvlink soc credits");
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val = readl_relaxed(soc1);
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writel_relaxed(val, soc1);
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val = readl_relaxed(soc1 + 4);
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writel_relaxed(val, soc1 + 4);
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val = readl_relaxed(soc2);
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writel_relaxed(val, soc2);
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val = readl_relaxed(soc2 + 4);
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writel_relaxed(val, soc2 + 4);
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val = readl_relaxed(soc3);
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writel_relaxed(val, soc3);
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val = readl_relaxed(soc3 + 4);
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writel_relaxed(val, soc3 + 4);
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val = readl_relaxed(soc4);
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writel_relaxed(val, soc4);
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val = readl_relaxed(soc4 + 4);
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writel_relaxed(val, soc4 + 4);
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}
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int nvgpu_nvlink_deinit(struct gk20a *g)
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{
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#ifdef CONFIG_TEGRA_NVLINK
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struct nvlink_device *ndev = g->nvlink.priv;
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int err;
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK))
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return -ENODEV;
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err = nvlink_shutdown(ndev);
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if (err) {
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nvgpu_err(g, "failed to shut down nvlink");
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return err;
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}
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nvgpu_nvlink_remove(g);
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return 0;
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#endif
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return -ENODEV;
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}
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