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96bea78d55
Add following two HALs to ce gops: - init_hw: Build a list of non-stall interrupt vectors and register them with struct nvgpu_mc. - intr_enable: Enable ce engine stall, non-stall interrupts. Jira: NVGPU-5034 Change-Id: Ibdc768c2bce778237233803ebbbd5190362b4578 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329166 Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
85 lines
2.6 KiB
C
85 lines
2.6 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/ce.h>
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#include <nvgpu/power_features/cg.h>
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#include <nvgpu/gops_mc.h>
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#include <nvgpu/mc.h>
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int nvgpu_ce_init_support(struct gk20a *g)
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{
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u32 ce_reset_mask;
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#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
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int err = 0;
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#endif
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if (g->ops.ce.set_pce2lce_mapping != NULL) {
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g->ops.ce.set_pce2lce_mapping(g);
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}
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#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
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if (g->ops.mc.reset_engine != NULL) {
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err = nvgpu_next_mc_reset_engine(g, NVGPU_ENGINE_GRCE);
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if (err != 0) {
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nvgpu_err(g, "NVGPU_ENGINE_GRCE reset failed");
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return err;
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}
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err = nvgpu_next_mc_reset_engine(g, NVGPU_ENGINE_ASYNC_CE);
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if (err != 0) {
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nvgpu_err(g, "NVGPU_ENGINE_ASYNC_CE reset failed");
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return err;
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}
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} else {
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#endif
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ce_reset_mask = nvgpu_engine_get_all_ce_reset_mask(g);
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g->ops.mc.reset(g, ce_reset_mask);
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#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
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}
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#endif
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nvgpu_cg_slcg_ce2_load_enable(g);
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nvgpu_cg_blcg_ce_load_enable(g);
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if (g->ops.ce.init_prod_values != NULL) {
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g->ops.ce.init_prod_values(g);
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}
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if (g->ops.ce.init_hw != NULL) {
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g->ops.ce.init_hw(g);
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}
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if (g->ops.ce.intr_enable != NULL) {
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g->ops.ce.intr_enable(g, true);
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}
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/** Enable interrupts at MC level */
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nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_CE, MC_INTR_ENABLE);
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nvgpu_mc_intr_nonstall_unit_config(g, MC_INTR_UNIT_CE, MC_INTR_ENABLE);
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return 0;
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}
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