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Error logging bits within the nvlink blocks like TLC and MIF are persistent through reset, to enable them to be polled following a reset event. That means that they are in an unknown state at cold reset, and may contain error state after a warm reset event. Software is expected to reset them, either by writing ones to the status bits or by writing to the DEBUG_RESET register at the IOCTRL top level, to clear the state out before enabling error reporting. JIRA NVGPU-4352 Change-Id: Iab4e96388fd827c0d694eada61b20f24bbddd1ff Signed-off-by: tkudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317683 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>