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2f712e2230
- Updated falcon controller HAL to support SEC2 falcon & used "is_falcon_supported" flag to know the support on chip. - Created falcon HAL flcn_gp106.c/h under gp106 to enable support for SEC2 & inherited gk20a flcn support. - Deleted SEC2 falcon related methods to make use of generic flacon controller methods for SEC2. - GP106 SEC2 code cleanup NVPU JIRA-99 Change-Id: I846e8015ed33554b3d8a45795314f1d28eee482f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1510200 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
20 lines
705 B
C
20 lines
705 B
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __FLCN_GK20A_H__
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#define __FLCN_GK20A_H__
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void gk20a_falcon_ops(struct nvgpu_falcon *flcn);
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void gk20a_falcon_init_hal(struct gpu_ops *gops);
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#endif /* __FLCN_GK20A_H__ */
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