Files
linux-nvgpu/drivers/gpu/nvgpu/gp106/sec2_gp106.h
Sagar Kamble 84b493e644 gpu: nvgpu: update SEC2 falcon base addr init
SEC2 falcon base address was being set without invoking hal api. Remove
FALCON_SEC_BASE. This patch defines gpu_ops.sec2.falcon_base_addr hal api
to get this base address.
Also, don't initialize the base for non-supported falcons.

JIRA NVGPU-1587

Change-Id: Iad19a9987416076cf9090d30a48ff83369cf73c2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969429
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-12-12 15:14:13 -08:00

35 lines
1.4 KiB
C

/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_SEC2_GP106_H
#define NVGPU_SEC2_GP106_H
int gp106_sec2_reset(struct gk20a *g);
int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g,
struct hs_acr *acr_desc,
struct nvgpu_falcon_bl_info *bl_info);
u32 gp106_sec2_falcon_base_addr(void);
#endif /* NVGPU_SEC2_GP106_H */