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c6e021589e
Changes between GV100 and Turing VFE pstate tables- 1. PS3.5 ucode packs two sets of vfe boardobjgrp - primary and rppm in new struct whose name is appended with suffix pack. The rppm (runtime power and performance model) set is needed to achieve Max Q. The rppm set is not relevant to Automotive SKUs and entries are set to 'disabled'. But the turing ucode in R400 uses the 'pack' struct to calculate supersurface offset and size of vfe_var/equ boardobjgrp. 2. Header size has been increased to add RPPM related VFE variable and equation count. VFE Variables boardobjgrp specific changes- 1. New var type 'single caller specified' had been added to represent generic type of variable which is not associated with voltage or frequency but identified by a Unique ID. 2. The frequency variable type can be associated with a clock domain, if the clock domain index availability flag is set. VFE Equations boardobjgrp specific changes- 1. New entry type 'scalar' had been added to allow scaling equation pointed by 'equ_idx_to_scale'. 2. More ouput types are added to represent the equation evaluation results. We modify the nvgpu Turing driver and GV100 ucode to adapt to these changes. This patch also fixes some MISRA defects in touched files. JIRA NVGPU-1178 Change-Id: I90910ac8dccf0b98a588cbc442dc11ac4fbd2e61 Signed-off-by: tkudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1928999 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com> Tested-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
97 lines
4.4 KiB
C
97 lines
4.4 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PERF_H
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#define NVGPU_PERF_H
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include "vfe_equ.h"
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#include "vfe_var.h"
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#include "pstate/pstate.h"
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#include "volt/volt.h"
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#include "lpwr/lpwr.h"
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#include "change_seq.h"
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#define CTRL_PERF_VFE_VAR_TYPE_INVALID 0x00U
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#define CTRL_PERF_VFE_VAR_TYPE_DERIVED 0x01U
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#define CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT 0x02U
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#define CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM 0x03U
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#define CTRL_PERF_VFE_VAR_TYPE_SINGLE 0x04U
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#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY 0x05U
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#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED 0x06U
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#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE 0x07U
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#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP 0x08U
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#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE 0x09U
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#define CTRL_PERF_VFE_VAR_TYPE_SINGLE_CALLER_SPECIFIED 0x0AU
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#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_NONE 0x00U
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#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_VALUE 0x01U
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#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_OFFSET 0x02U
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#define CTRL_PERF_VFE_VAR_SINGLE_OVERRIDE_TYPE_SCALE 0x03U
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#define CTRL_PERF_VFE_EQU_TYPE_INVALID 0x00U
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#define CTRL_PERF_VFE_EQU_TYPE_COMPARE 0x01U
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#define CTRL_PERF_VFE_EQU_TYPE_MINMAX 0x02U
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#define CTRL_PERF_VFE_EQU_TYPE_QUADRATIC 0x03U
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#define CTRL_PERF_VFE_EQU_TYPE_SCALAR 0x04U
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_UNITLESS 0x00U
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_FREQ_MHZ 0x01U
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VOLT_UV 0x02U
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VF_GAIN 0x03U
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VOLT_DELTA_UV 0x04U
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_WORK_TYPE 0x06U
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_UTIL_RATIO 0x07U
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_WORK_FB_NORM 0x08U
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_POWER_MW 0x09U
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_PWR_OVER_UTIL_SLOPE 0x0AU
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#define CTRL_PERF_VFE_EQU_OUTPUT_TYPE_VIN_CODE 0x0BU
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#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03U
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#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_EQUAL 0x00U
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#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_GREATER_EQ 0x01U
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#define CTRL_PERF_VFE_EQU_COMPARE_FUNCTION_GREATER 0x02U
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struct gk20a;
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struct nvgpu_vfe_invalidate {
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bool state_change;
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struct nvgpu_cond wq;
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struct nvgpu_thread state_task;
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};
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struct perf_pmupstate {
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struct vfe_vars vfe_varobjs;
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struct vfe_equs vfe_equobjs;
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struct pstates pstatesobjs;
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struct obj_volt volt;
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struct obj_lwpr lpwr;
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struct nvgpu_vfe_invalidate vfe_init;
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struct change_seq_pmu changeseq_pmu;
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};
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int perf_pmu_init_pmupstate(struct gk20a *g);
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void perf_pmu_free_pmupstate(struct gk20a *g);
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int perf_pmu_vfe_load(struct gk20a *g);
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#endif /* NVGPU_PERF_H */
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