mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
200777b854
Below changes are added.
1) Added checks in
nvgpu_channel_from_id__func, nvgpu_tsg_check_and_get_from_id
2) Added BVEC tests for
nvgpu_channel_open_new, nvgpu_channel_from_id,
nvgpu_tsg_check_and_get_from_id, nvgpu_tsg_set_error_notifier
3) Added common function get_random_u32.
Jira NVGPU-6905
Change-Id: I374d6f5503dc05e3224213d772a1752d82cbdc91
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548304
(cherry picked from commit 39b2529b3e96cfd3cbd3bb020f32ee2cca0ea363)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554021
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
162 lines
5.1 KiB
Makefile
162 lines
5.1 KiB
Makefile
# -*- mode: makefile -*-
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#
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# Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a
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# copy of this software and associated documentation files (the "Software"),
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# to deal in the Software without restriction, including without limitation
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# the rights to use, copy, modify, merge, publish, distribute, sublicense,
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# and/or sell copies of the Software, and to permit persons to whom the
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# Software is furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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# DEALINGS IN THE SOFTWARE.
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include $(NVGPU_SRC)/Makefile.sources
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include $(NVGPU_NEXT_SRC)/Makefile.sources
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OBJS := $(srcs:%.c=$(NVGPU_OUT)/%.o) $(srcs_next:%.c=$(NVGPU_OUT)/%.o)
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HEADERS := \
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$(NVGPU_SRC)/include/nvgpu/*.h \
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$(NVGPU_SRC)/include/nvgpu/hw/*/*.h
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CORE_OBJS := \
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$(CORE_OUT)/unit_main.o \
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$(CORE_OUT)/nvgpu.o \
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$(CORE_OUT)/args.o \
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$(CORE_OUT)/io.o \
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$(CORE_OUT)/module.o \
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$(CORE_OUT)/required_tests.o \
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$(CORE_OUT)/results.o \
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$(CORE_OUT)/exec.o \
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$(CORE_OUT)/utils.o
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CORE_HEADERS := \
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$(CORE_SRC)/../include/unit/*.h
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# Each directory under the UNIT_SRC directory should correspond to one module.
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UNITS := \
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$(UNIT_SRC)/posix/env \
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$(UNIT_SRC)/posix/bitops \
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$(UNIT_SRC)/posix/fault-injection \
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$(UNIT_SRC)/posix/bug \
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$(UNIT_SRC)/posix/os_sched \
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$(UNIT_SRC)/posix/log2 \
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$(UNIT_SRC)/posix/sizes \
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$(UNIT_SRC)/posix/thread \
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$(UNIT_SRC)/posix/cond \
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$(UNIT_SRC)/posix/timers \
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$(UNIT_SRC)/posix/kmem \
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$(UNIT_SRC)/posix/rwsem \
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$(UNIT_SRC)/posix/queue \
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$(UNIT_SRC)/posix/utils \
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$(UNIT_SRC)/posix/circ_buf \
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$(UNIT_SRC)/bus \
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$(UNIT_SRC)/pramin \
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$(UNIT_SRC)/ptimer \
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$(UNIT_SRC)/priv_ring \
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$(UNIT_SRC)/init \
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$(UNIT_SRC)/interface/bit-utils \
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$(UNIT_SRC)/interface/lock \
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$(UNIT_SRC)/interface/nvgpu_gk20a \
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$(UNIT_SRC)/interface/atomic \
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$(UNIT_SRC)/interface/rbtree \
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$(UNIT_SRC)/interface/static_analysis \
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$(UNIT_SRC)/interface/string \
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$(UNIT_SRC)/interface/worker \
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$(UNIT_SRC)/interface/kref \
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$(UNIT_SRC)/interface/list \
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$(UNIT_SRC)/mc \
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$(UNIT_SRC)/mm/nvgpu_sgt \
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$(UNIT_SRC)/mm/allocators/buddy_allocator \
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$(UNIT_SRC)/mm/allocators/nvgpu_allocator \
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$(UNIT_SRC)/mm/allocators/bitmap_allocator \
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$(UNIT_SRC)/mm/allocators/page_allocator \
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$(UNIT_SRC)/mm/as \
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$(UNIT_SRC)/mm/dma \
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$(UNIT_SRC)/mm/gmmu/pd_cache \
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$(UNIT_SRC)/mm/gmmu/page_table \
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$(UNIT_SRC)/mm/hal/cache/flush_gk20a_fusa \
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$(UNIT_SRC)/mm/hal/cache/flush_gv11b_fusa \
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$(UNIT_SRC)/mm/hal/gmmu/gmmu_gk20a_fusa \
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$(UNIT_SRC)/mm/hal/gmmu/gmmu_gm20b_fusa \
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$(UNIT_SRC)/mm/hal/gmmu/gmmu_gp10b_fusa \
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$(UNIT_SRC)/mm/hal/gmmu/gmmu_gv11b_fusa \
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$(UNIT_SRC)/mm/hal/gp10b_fusa \
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$(UNIT_SRC)/mm/hal/gv11b_fusa \
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$(UNIT_SRC)/mm/hal/mmu_fault/gv11b_fusa \
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$(UNIT_SRC)/mm/mm \
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$(UNIT_SRC)/mm/page_table_faults \
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$(UNIT_SRC)/mm/nvgpu_mem \
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$(UNIT_SRC)/mm/vm \
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$(UNIT_SRC)/netlist \
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$(UNIT_SRC)/fb \
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$(UNIT_SRC)/fbp \
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$(UNIT_SRC)/fifo \
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$(UNIT_SRC)/fifo/fifo/gk20a \
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$(UNIT_SRC)/fifo/fifo/gv11b \
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$(UNIT_SRC)/fifo/channel \
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$(UNIT_SRC)/fifo/channel/gk20a \
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$(UNIT_SRC)/fifo/channel/gm20b \
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$(UNIT_SRC)/fifo/channel/gv11b \
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$(UNIT_SRC)/fifo/ctxsw_timeout/gv11b \
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$(UNIT_SRC)/fifo/engine \
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$(UNIT_SRC)/fifo/engine/gm20b \
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$(UNIT_SRC)/fifo/engine/gp10b \
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$(UNIT_SRC)/fifo/engine/gv100 \
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$(UNIT_SRC)/fifo/engine/gv11b \
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$(UNIT_SRC)/fifo/fifo \
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$(UNIT_SRC)/fifo/pbdma \
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$(UNIT_SRC)/fifo/pbdma/gm20b \
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$(UNIT_SRC)/fifo/pbdma/gp10b \
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$(UNIT_SRC)/fifo/pbdma/gv11b \
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$(UNIT_SRC)/fifo/preempt \
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$(UNIT_SRC)/fifo/preempt/gv11b \
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$(UNIT_SRC)/fifo/ramfc/gp10b \
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$(UNIT_SRC)/fifo/ramfc/gv11b \
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$(UNIT_SRC)/fifo/ramin/gk20a \
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$(UNIT_SRC)/fifo/ramin/gm20b \
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$(UNIT_SRC)/fifo/ramin/gv11b \
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$(UNIT_SRC)/fifo/runlist \
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$(UNIT_SRC)/fifo/runlist/gk20a \
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$(UNIT_SRC)/fifo/runlist/gv11b \
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$(UNIT_SRC)/fifo/tsg \
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$(UNIT_SRC)/fifo/tsg/gv11b \
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$(UNIT_SRC)/fifo/userd/gk20a \
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$(UNIT_SRC)/fifo/usermode/gv11b \
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$(UNIT_SRC)/ltc \
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$(UNIT_SRC)/enabled \
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$(UNIT_SRC)/falcon \
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$(UNIT_SRC)/falcon/falcon_tests \
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$(UNIT_SRC)/fuse \
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$(UNIT_SRC)/pmu \
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$(UNIT_SRC)/therm \
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$(UNIT_SRC)/top \
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$(UNIT_SRC)/class \
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$(UNIT_SRC)/gr \
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$(UNIT_SRC)/gr/falcon \
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$(UNIT_SRC)/gr/config \
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$(UNIT_SRC)/gr/init \
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$(UNIT_SRC)/gr/fs_state \
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$(UNIT_SRC)/gr/global_ctx \
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$(UNIT_SRC)/gr/ctx \
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$(UNIT_SRC)/gr/obj_ctx \
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$(UNIT_SRC)/gr/intr \
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$(UNIT_SRC)/gr/setup \
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$(UNIT_SRC)/acr \
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$(UNIT_SRC)/ce \
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$(UNIT_SRC)/cg \
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$(UNIT_SRC)/rc \
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$(UNIT_SRC)/sync \
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$(UNIT_SRC)/ecc \
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$(UNIT_SRC)/io
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