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3ef8e6b099
Add three hals in gr.falcon - fecs_host_intr_status This reads the fecs_host_intr_status, set the variables in the nvgpu_fecs_host_intr_status struct to report back for gr to handle the interrupts properly - fecs_host_clear_intr This helps to clear the needed bits in fecs_host_intr. - read_fecs_ctxsw_mailbox This reads the ctxsw_mailbox register based on register index. Use these hals in gk20a_gr_handle_fecs_error and gp10b_gr_handle_fecs_error functions. JIRA NVGPU-1881 Change-Id: Ia02a254acc38e7e25c7c3605e9f1dda4da898543 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2093917 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>