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1170687c33
When using a coherent DMA API wee must make sure to program any aperture fields with the coherent aperture setting. To do this the nvgpu_aperture_mask() function was modified to take a third aperture mask argument, a coherent setting, so that code can use this function to generate coherent aperture settings. The aperture choice is some what tricky: the default version of this function uses the state of the DMA API to determine what aperture to use for SYSMEM: either coherent or non-coherent internally. Thus a kernel user need only specify the normal nvgpu_mem struct and the correct mask should be chosen. Due to many uses of nvgpu_mem structs not created directly from the DMA API wrapper it's easier to translate SYSMEM to SYSMEM_COH after creation. However, the GMMU mapping code, will encounter buffers from userspace with difference coerency attributes than the DMA API. Thus the __nvgpu_aperture_mask() really respects the aperture setting passed in regardless of the DMA API state. This aperture setting is pulled from NVGPU_VM_MAP_IO_COHERENT since this is either passed in from userspace or set by the kernel when using coherent DMA. The aperture field in attrs is upgraded to coh if this flag is set. This change also adds a coherent sysmem mask everywhere that it can. There's a couple places that do not have a coherent register field defined yet. These need to eventually be defined and added. Lastly the aperture mask code has been mvoed from the Linux vm.c code to the general vm.c code since this function has no Linux dependencies. Note: depends on https://git-master.nvidia.com/r/1664536 for new register fields. JIRA EVLR-2333 Change-Id: I4b347911ecb7c511738563fe6c34d0e6aa380d71 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1655220 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
123 lines
3.6 KiB
C
123 lines
3.6 KiB
C
/*
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* GK20A memory interface
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <trace/events/gk20a.h>
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#include "gk20a.h"
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#include "fb_gk20a.h"
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#include <nvgpu/timers.h>
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#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
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void fb_gk20a_reset(struct gk20a *g)
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{
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u32 val;
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gk20a_dbg_info("reset gk20a fb");
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g->ops.mc.reset(g, mc_enable_pfb_enabled_f() |
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mc_enable_l2_enabled_f() |
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mc_enable_xbar_enabled_f() |
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mc_enable_hub_enabled_f());
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val = gk20a_readl(g, mc_elpg_enable_r());
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val |= mc_elpg_enable_xbar_enabled_f()
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| mc_elpg_enable_pfb_enabled_f()
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| mc_elpg_enable_hub_enabled_f();
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gk20a_writel(g, mc_elpg_enable_r(), val);
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}
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void gk20a_fb_init_hw(struct gk20a *g)
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{
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u32 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8;
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gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), addr);
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}
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void gk20a_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
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{
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struct nvgpu_timeout timeout;
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u32 addr_lo;
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u32 data;
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gk20a_dbg_fn("");
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/* pagetables are considered sw states which are preserved after
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prepare_poweroff. When gk20a deinit releases those pagetables,
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common code in vm unmap path calls tlb invalidate that touches
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hw. Use the power_on flag to skip tlb invalidation when gpu
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power is turned off */
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if (!g->power_on)
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return;
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addr_lo = u64_lo32(nvgpu_mem_get_addr(g, pdb) >> 12);
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nvgpu_mutex_acquire(&g->mm.tlb_lock);
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trace_gk20a_mm_tlb_invalidate(g->name);
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nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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do {
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data = gk20a_readl(g, fb_mmu_ctrl_r());
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if (fb_mmu_ctrl_pri_fifo_space_v(data) != 0)
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break;
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nvgpu_udelay(2);
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} while (!nvgpu_timeout_expired_msg(&timeout,
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"wait mmu fifo space"));
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if (nvgpu_timeout_peek_expired(&timeout))
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goto out;
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nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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gk20a_writel(g, fb_mmu_invalidate_pdb_r(),
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fb_mmu_invalidate_pdb_addr_f(addr_lo) |
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nvgpu_aperture_mask(g, pdb,
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fb_mmu_invalidate_pdb_aperture_sys_mem_f(),
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fb_mmu_invalidate_pdb_aperture_sys_mem_f(),
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fb_mmu_invalidate_pdb_aperture_vid_mem_f()));
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gk20a_writel(g, fb_mmu_invalidate_r(),
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fb_mmu_invalidate_all_va_true_f() |
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fb_mmu_invalidate_trigger_true_f());
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do {
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data = gk20a_readl(g, fb_mmu_ctrl_r());
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if (fb_mmu_ctrl_pri_fifo_empty_v(data) !=
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fb_mmu_ctrl_pri_fifo_empty_false_f())
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break;
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nvgpu_udelay(2);
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} while (!nvgpu_timeout_expired_msg(&timeout,
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"wait mmu invalidate"));
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trace_gk20a_mm_tlb_invalidate_done(g->name);
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out:
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nvgpu_mutex_release(&g->mm.tlb_lock);
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}
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