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39a9e251da
This change adds a new sysfs node to allow configuring CZF_BYPASS, to
enable platforms with low context-switching latency requirements.
/sys/devices/17000000.gp10b/czf_bypass
Values:
0 - always
1 - lateZ (default)
2 - single pass
3 - never
The specified value will apply only to newly allocated contexts.
Bug 1914014
Change-Id: Ibb9a8e86089acaadaa7260b00eedec5c80762d6f
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1478567
(cherry picked from commit 3bc022cb38)
Reviewed-on: http://git-master/r/1473820
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
100 lines
2.5 KiB
C
100 lines
2.5 KiB
C
/*
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* GP10B specific sysfs files
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*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/platform_device.h>
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#include "gk20a/gk20a.h"
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#include "gp10b_sysfs.h"
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#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
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#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH)
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static ssize_t ecc_enable_store(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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struct gk20a *g = get_gk20a(dev);
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u32 ecc_mask;
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u32 err = 0;
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err = sscanf(buf, "%d", &ecc_mask);
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if (err == 1) {
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err = g->ops.pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd
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(g, ecc_mask);
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if (err)
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nvgpu_err(g, "ECC override did not happen\n");
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} else
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return -EINVAL;
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return count;
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}
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static ssize_t ecc_enable_read(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct gk20a *g = get_gk20a(dev);
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return sprintf(buf, "ecc override =0x%x\n",
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g->ops.gr.get_lrf_tex_ltc_dram_override(g));
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}
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static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store);
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static ssize_t czf_bypass_store(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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struct gk20a *g = get_gk20a(dev);
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unsigned long val;
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if (kstrtoul(buf, 10, &val) < 0)
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return -EINVAL;
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if (val >= 4)
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return -EINVAL;
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g->gr.czf_bypass = val;
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return count;
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}
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static ssize_t czf_bypass_read(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct gk20a *g = get_gk20a(dev);
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return sprintf(buf, "%d\n", g->gr.czf_bypass);
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}
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static DEVICE_ATTR(czf_bypass, ROOTRW, czf_bypass_read, czf_bypass_store);
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void gp10b_create_sysfs(struct device *dev)
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{
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struct gk20a *g = get_gk20a(dev);
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int error = 0;
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g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v();
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error |= device_create_file(dev, &dev_attr_ecc_enable);
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error |= device_create_file(dev, &dev_attr_czf_bypass);
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if (error)
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nvgpu_err(g, "Failed to create sysfs attributes!\n");
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}
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void gp10b_remove_sysfs(struct device *dev)
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{
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device_remove_file(dev, &dev_attr_ecc_enable);
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device_remove_file(dev, &dev_attr_czf_bypass);
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}
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