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e5a762c637
Added SW_THRESHOLD policy support for over power protection. JIRA DNVGPU-70 Change-Id: I021f47f234d42be15ddbfd02a22e9299fd486636 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1233051 (cherry picked from commit 301e0ac123a7a65a7f83e5615f3a89e55253a0bd) Reviewed-on: http://git-master/r/1241958 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
/*
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* Control pmgr state infrastructure
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ctrlpmgr_h_
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#define _ctrlpmgr_h_
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#include "ctrlboardobj.h"
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/* valid power domain values */
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#define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32
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#define CTRL_PMGR_PWR_VIOLATION_MAX 0x06
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#define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221 0x4E
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#define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID 0xFF
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#define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR 0x08
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#define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X 0x30
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#define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD 0x04
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#define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD 0x0C
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#define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS 0x8
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#define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES 0x08
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#define CTRL_PMGR_PWR_POLICY_INDEX_INVALID 0xFF
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#define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM 0xFE
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#define CTRL_PMGR_PWR_POLICY_LIMIT_MAX (0xFFFFFFFF)
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struct ctrl_pmgr_pwr_device_info_rshunt {
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bool use_fxp8_8;
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u16 rshunt_value;
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};
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struct ctrl_pmgr_pwr_policy_info_integral {
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u8 past_sample_count;
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u8 next_sample_count;
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u16 ratio_limit_min;
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u16 ratio_limit_max;
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};
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enum ctrl_pmgr_pwr_policy_filter_type {
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CTRL_PMGR_PWR_POLICY_FILTER_TYPE_NONE = 0,
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CTRL_PMGR_PWR_POLICY_FILTER_TYPE_BLOCK,
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CTRL_PMGR_PWR_POLICY_FILTER_TYPE_MOVING_AVERAGE,
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CTRL_PMGR_PWR_POLICY_FILTER_TYPE_IIR
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};
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struct ctrl_pmgr_pwr_policy_filter_param_block {
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u32 block_size;
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};
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struct ctrl_pmgr_pwr_policy_filter_param_moving_average {
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u32 window_size;
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};
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struct ctrl_pmgr_pwr_policy_filter_param_iir {
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u32 divisor;
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};
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union ctrl_pmgr_pwr_policy_filter_param {
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struct ctrl_pmgr_pwr_policy_filter_param_block block;
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struct ctrl_pmgr_pwr_policy_filter_param_moving_average moving_avg;
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struct ctrl_pmgr_pwr_policy_filter_param_iir iir;
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};
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struct ctrl_pmgr_pwr_policy_limit_input {
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u8 pwr_policy_idx;
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u32 limit_value;
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};
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struct ctrl_pmgr_pwr_policy_limit_arbitration {
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bool b_arb_max;
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u8 num_inputs;
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u32 output;
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struct ctrl_pmgr_pwr_policy_limit_input
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inputs[CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS];
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};
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#endif
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