rmylavarapu 89eec35887 gpu: nvgpu: Disable VFE secondary entry in clk_prog obj ...

As support of VFE secondary entry is not POR for tu10a
profile need to disable this in our NVGPU. If not the
clkDomainsIsSecVFCurvesEnabled() check in PMU firmware
will hit an halt.

JIRA NVGPU-3810

Change-Id: Id72550393a0255e7c663c3fde0bbbdcef2d5885e
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153124
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-07-29 05:30:15 -07:00

..

clk_domain.c

gpu: nvgpu: Change clk load command to RPC

2019-07-29 05:28:20 -07:00

clk_domain.h

gpu: nvgpu: Clock domain board_objs for chips_a fw

2019-07-29 05:27:54 -07:00

clk_fll.c

gpu: nvgpu: Clk_vin board_obj support.

2019-07-29 05:28:07 -07:00

clk_freq_controller.c

gpu: nvgpu: Change freq_controller load from cmd to rpc

2019-07-29 05:28:33 -07:00

clk_freq_controller.h

gpu: nvgpu: fix MISRA rule 5.7 and 4.7 violations

2019-04-13 12:34:01 -07:00

clk_freq_domain.c

gpu: nvgpu: alloc space for PMU's struct nvgpu_pmu at runtime

2019-05-23 00:56:55 -07:00

clk_prog.c

gpu: nvgpu: Disable VFE secondary entry in clk_prog obj

2019-07-29 05:30:15 -07:00

clk_prog.h

gpu: nvgpu: Fix MISRA viaolation in clk_prog unit

2019-05-06 04:05:59 -07:00

clk_vf_point.c

gpu: nvgpu: alloc space for PMU's struct nvgpu_pmu at runtime

2019-05-23 00:56:55 -07:00

clk_vin.c

gpu: nvgpu: Clk_vin board_obj support.

2019-07-29 05:28:07 -07:00

clk_vin.h

gpu: nvgpu: Clean clk_vin unit

2019-04-08 17:33:54 -07:00

clk.c

gpu: nvgpu: Clk_vin board_obj support.

2019-07-29 05:28:07 -07:00