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fd332ca6b4
There is mixed usage of falcon & flcn in function and data types. Lets update all with "falcon" for consistency with file names. JIRA NVGPU-1459 Change-Id: I02dbc866ce2cca009f2e8b87cfe11a919ec10749 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1953793 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
272 lines
6.6 KiB
C
272 lines
6.6 KiB
C
/*
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bios.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/falcon.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "gm20b/fifo_gm20b.h"
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#include "bios_gp106.h"
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#include "gp106/mclk_gp106.h"
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#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
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#include <nvgpu/hw/gp106/hw_top_gp106.h>
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#define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */
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#define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */
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#define BIOS_OVERLAY_NAME "bios-%04x.rom"
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#define BIOS_OVERLAY_NAME_FORMATTED "bios-xxxx.rom"
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#define ROM_FILE_PAYLOAD_OFFSET 0xa00
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#define BIOS_SIZE 0x90000
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static void upload_code(struct gk20a *g, u32 dst,
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u8 *src, u32 size, u8 port, bool sec)
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{
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nvgpu_falcon_copy_to_imem(g->pmu.flcn, dst, src, size, port, sec,
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dst >> 8);
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}
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static void upload_data(struct gk20a *g, u32 dst, u8 *src, u32 size, u8 port)
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{
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u32 i, words;
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u32 *src_u32 = (u32 *)src;
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u32 blk;
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nvgpu_log_info(g, "upload %d bytes to %x", size, dst);
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words = DIV_ROUND_UP(size, 4);
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blk = dst >> 8;
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nvgpu_log_info(g, "upload %d words to %x blk %d",
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words, dst, blk);
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gk20a_writel(g, pwr_falcon_dmemc_r(port),
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pwr_falcon_dmemc_offs_f(dst >> 2) |
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pwr_falcon_dmemc_blk_f(blk) |
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pwr_falcon_dmemc_aincw_f(1));
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for (i = 0; i < words; i++) {
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gk20a_writel(g, pwr_falcon_dmemd_r(port), src_u32[i]);
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}
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}
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int gp106_bios_devinit(struct gk20a *g)
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{
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int err = 0;
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bool devinit_completed;
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struct nvgpu_timeout timeout;
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nvgpu_log_fn(g, " ");
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if (nvgpu_falcon_reset(g->pmu.flcn) != 0) {
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err = -ETIMEDOUT;
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goto out;
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}
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upload_code(g, g->bios.devinit.bootloader_phys_base,
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g->bios.devinit.bootloader,
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g->bios.devinit.bootloader_size,
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0, 0);
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upload_code(g, g->bios.devinit.phys_base,
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g->bios.devinit.ucode,
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g->bios.devinit.size,
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0, 1);
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upload_data(g, g->bios.devinit.dmem_phys_base,
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g->bios.devinit.dmem,
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g->bios.devinit.dmem_size,
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0);
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upload_data(g, g->bios.devinit_tables_phys_base,
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g->bios.devinit_tables,
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g->bios.devinit_tables_size,
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0);
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upload_data(g, g->bios.devinit_script_phys_base,
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g->bios.bootscripts,
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g->bios.bootscripts_size,
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0);
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nvgpu_falcon_bootstrap(g->pmu.flcn, g->bios.devinit.code_entry_point);
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nvgpu_timeout_init(g, &timeout,
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PMU_BOOT_TIMEOUT_MAX /
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PMU_BOOT_TIMEOUT_DEFAULT,
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NVGPU_TIMER_RETRY_TIMER);
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do {
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devinit_completed = (pwr_falcon_cpuctl_halt_intr_v(
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gk20a_readl(g, pwr_falcon_cpuctl_r())) != 0U) &&
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(top_scratch1_devinit_completed_v(
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gk20a_readl(g, top_scratch1_r())) != 0U);
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nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
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} while (!devinit_completed && (nvgpu_timeout_expired(&timeout) == 0));
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if (nvgpu_timeout_peek_expired(&timeout) != 0) {
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err = -ETIMEDOUT;
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}
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nvgpu_falcon_clear_halt_intr_status(g->pmu.flcn,
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gk20a_get_gr_idle_timeout(g));
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out:
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nvgpu_log_fn(g, "done");
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return err;
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}
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int gp106_bios_preos_wait_for_halt(struct gk20a *g)
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{
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int err = 0;
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if (nvgpu_falcon_wait_for_halt(g->pmu.flcn,
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PMU_BOOT_TIMEOUT_MAX / 1000) != 0) {
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err = -ETIMEDOUT;
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}
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return err;
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}
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int gp106_bios_preos(struct gk20a *g)
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{
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int err = 0;
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nvgpu_log_fn(g, " ");
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if (nvgpu_falcon_reset(g->pmu.flcn) != 0) {
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err = -ETIMEDOUT;
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goto out;
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}
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if (g->ops.bios.preos_reload_check != NULL) {
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g->ops.bios.preos_reload_check(g);
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}
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upload_code(g, g->bios.preos.bootloader_phys_base,
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g->bios.preos.bootloader,
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g->bios.preos.bootloader_size,
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0, 0);
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upload_code(g, g->bios.preos.phys_base,
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g->bios.preos.ucode,
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g->bios.preos.size,
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0, 1);
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upload_data(g, g->bios.preos.dmem_phys_base,
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g->bios.preos.dmem,
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g->bios.preos.dmem_size,
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0);
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nvgpu_falcon_bootstrap(g->pmu.flcn, g->bios.preos.code_entry_point);
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err = g->ops.bios.preos_wait_for_halt(g);
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nvgpu_falcon_clear_halt_intr_status(g->pmu.flcn,
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gk20a_get_gr_idle_timeout(g));
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out:
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nvgpu_log_fn(g, "done");
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return err;
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}
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int gp106_bios_init(struct gk20a *g)
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{
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unsigned int i;
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int err;
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nvgpu_log_fn(g, " ");
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if (g->bios_is_init) {
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return 0;
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}
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nvgpu_log_info(g, "reading bios from EEPROM");
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g->bios.size = BIOS_SIZE;
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g->bios.data = nvgpu_vmalloc(g, BIOS_SIZE);
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if (g->bios.data == NULL) {
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return -ENOMEM;
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}
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if (g->ops.xve.disable_shadow_rom != NULL) {
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g->ops.xve.disable_shadow_rom(g);
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}
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for (i = 0; i < g->bios.size/4; i++) {
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u32 val = be32_to_cpu(gk20a_readl(g, 0x300000 + i*4));
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g->bios.data[(i*4)] = (val >> 24) & 0xff;
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g->bios.data[(i*4)+1] = (val >> 16) & 0xff;
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g->bios.data[(i*4)+2] = (val >> 8) & 0xff;
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g->bios.data[(i*4)+3] = val & 0xff;
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}
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if (g->ops.xve.enable_shadow_rom != NULL) {
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g->ops.xve.enable_shadow_rom(g);
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}
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err = nvgpu_bios_parse_rom(g);
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if (err != 0) {
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goto free_firmware;
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}
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if (g->bios.vbios_version < g->vbios_min_version) {
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nvgpu_err(g, "unsupported VBIOS version %08x",
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g->bios.vbios_version);
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err = -EINVAL;
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goto free_firmware;
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} else {
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nvgpu_info(g, "VBIOS version %08x", g->bios.vbios_version);
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}
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nvgpu_log_fn(g, "done");
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if (g->ops.bios.devinit != NULL) {
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err = g->ops.bios.devinit(g);
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if (err != 0) {
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nvgpu_err(g, "devinit failed");
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goto free_firmware;
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}
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}
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if (nvgpu_is_enabled(g, NVGPU_PMU_RUN_PREOS) &&
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(g->ops.bios.preos != NULL)) {
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err = g->ops.bios.preos(g);
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if (err != 0) {
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nvgpu_err(g, "pre-os failed");
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goto free_firmware;
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}
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}
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if (g->ops.bios.verify_devinit != NULL) {
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err = g->ops.bios.verify_devinit(g);
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if (err != 0) {
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nvgpu_err(g, "devinit status verification failed");
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goto free_firmware;
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}
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}
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g->bios_is_init = true;
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return 0;
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free_firmware:
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if (g->bios.data != NULL) {
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nvgpu_vfree(g, g->bios.data);
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}
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return err;
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}
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