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9e5f456f2b
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in gp10b by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: If66863e568d74a0bc7473cf8decacece1e1069f3 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1819163 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
45 lines
2.0 KiB
C
45 lines
2.0 KiB
C
/*
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*
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* Tegra GP10B GPU Debugger Driver Register Ops
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*
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_REGOPS_GP10B_H
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#define NVGPU_REGOPS_GP10B_H
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struct dbg_session_gk20a;
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const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void);
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u64 gp10b_get_global_whitelist_ranges_count(void);
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const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void);
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u64 gp10b_get_context_whitelist_ranges_count(void);
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const u32 *gp10b_get_runcontrol_whitelist(void);
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u64 gp10b_get_runcontrol_whitelist_count(void);
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const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void);
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u64 gp10b_get_runcontrol_whitelist_ranges_count(void);
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const u32 *gp10b_get_qctl_whitelist(void);
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u64 gp10b_get_qctl_whitelist_count(void);
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const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void);
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u64 gp10b_get_qctl_whitelist_ranges_count(void);
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int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
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#endif /* NVGPU_REGOPS_GP10B_H */
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