Konsta Holtta b0211379f0 gpu: nvgpu: cast usermode base explicitly to u64 ...

MISRA rule 10.6 forbids assignments of composite expressions to wider
essential types. Cast the u32 register addition to use u64 types
explicitly in tu104 usermode base address calculation.

Bug 200145225

Change-Id: I8f1535a21eba07bfbdf0a177fb9286e4c381aa2c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1949715
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2018-11-14 09:14:44 -08:00

8.7 KiB

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