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b368dc48b3
- Create nvlink_bios.c/.h files to separate out nvlink related bios code. - Create bios_sw_<chip speciific>.c/.h files to separate out chips specific bios code. - Create hal files for bios under hal/bios/ and move hardware specific code there. - Move hardware accessing hal files from common/top to hal/top JIRA NVGPU-2071 Change-Id: Ia466f1cd8947540b07b237e891312123df2c6b46 Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2107371 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
107 lines
3.4 KiB
C
107 lines
3.4 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bios.h>
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "bios_sw_gp106.h"
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#include "bios_sw_gv100.h"
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#define PMU_BOOT_TIMEOUT_DEFAULT 100U /* usec */
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#define PMU_BOOT_TIMEOUT_MAX 2000000U /* usec */
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#define SCRATCH_PREOS_PROGRESS 6U
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#define PREOS_PROGRESS_MASK(r) (((r) >> 12U) & 0xfU)
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#define PREOS_PROGRESS_NOT_STARTED 0U
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#define PREOS_PROGRESS_STARTED 1U
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#define PREOS_PROGRESS_EXIT 2U
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#define PREOS_PROGRESS_EXIT_SECUREMODE 3U
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#define PREOS_PROGRESS_ABORTED 6U
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#define SCRATCH_PMU_EXIT_AND_HALT 1U
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#define PMU_EXIT_AND_HALT_SET(r, v) (((r) & ~0x200U) | (v))
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#define PMU_EXIT_AND_HALT_YES BIT32(9)
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#define SCRATCH_PRE_OS_RELOAD 1U
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#define PRE_OS_RELOAD_SET(r, v) (((r) & ~0x100U) | (v))
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#define PRE_OS_RELOAD_YES BIT32(8)
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void gv100_bios_preos_reload_check(struct gk20a *g)
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{
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u32 progress = g->ops.bus.read_sw_scratch(g, SCRATCH_PREOS_PROGRESS);
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if (PREOS_PROGRESS_MASK(progress) != PREOS_PROGRESS_NOT_STARTED) {
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u32 reload = g->ops.bus.read_sw_scratch(g,
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SCRATCH_PRE_OS_RELOAD);
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g->ops.bus.write_sw_scratch(g, SCRATCH_PRE_OS_RELOAD,
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PRE_OS_RELOAD_SET(reload, PRE_OS_RELOAD_YES));
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}
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}
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int gv100_bios_preos_wait_for_halt(struct gk20a *g)
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{
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int err = -EINVAL;
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u32 progress;
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u32 tmp;
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bool preos_completed;
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struct nvgpu_timeout timeout;
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nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
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/* Check the progress */
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progress = g->ops.bus.read_sw_scratch(g, SCRATCH_PREOS_PROGRESS);
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if (PREOS_PROGRESS_MASK(progress) == PREOS_PROGRESS_STARTED) {
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err = 0;
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/* Complete the handshake */
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tmp = g->ops.bus.read_sw_scratch(g, SCRATCH_PMU_EXIT_AND_HALT);
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g->ops.bus.write_sw_scratch(g, SCRATCH_PMU_EXIT_AND_HALT,
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PMU_EXIT_AND_HALT_SET(tmp, PMU_EXIT_AND_HALT_YES));
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nvgpu_timeout_init(g, &timeout,
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PMU_BOOT_TIMEOUT_MAX /
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PMU_BOOT_TIMEOUT_DEFAULT,
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NVGPU_TIMER_RETRY_TIMER);
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do {
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progress = g->ops.bus.read_sw_scratch(g,
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SCRATCH_PREOS_PROGRESS);
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preos_completed = (g->ops.falcon.is_falcon_cpu_halted(
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&g->pmu.flcn) != 0U) &&
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(PREOS_PROGRESS_MASK(progress) ==
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PREOS_PROGRESS_EXIT);
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nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
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} while (!preos_completed &&
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(nvgpu_timeout_expired(&timeout) == 0));
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}
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return err;
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}
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