mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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53465def64
Most of BIOS parsing code is not specific to any particular GPU. Move most of the code to generic files, and leave only chip specific parts dealing with microcontroller boot into chip specific files. As most of the parsing is generic, they do not need to be called via HALs so remove the HALs and change the calls into direct function calls. All definitions meant to be used outside BIOS code itself are now in <nvgpu/bios.h> Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302222 GVS: Gerrit_Virtual_Submit
474 lines
13 KiB
C
474 lines
13 KiB
C
/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <nvgpu/bios.h>
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#include "gk20a/gk20a.h"
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#include "boardobj/boardobjgrp.h"
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#include "boardobj/boardobjgrp_e32.h"
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#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
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#include "ctrl/ctrlvolt.h"
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#include "gm206/bios_gm206.h"
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#include "gk20a/pmu_gk20a.h"
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#include "clk.h"
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#include "clk_vin.h"
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#include <nvgpu/hw/gp106/hw_fuse_gp106.h>
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static u32 devinit_get_vin_device_table(struct gk20a *g,
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struct avfsvinobjs *pvinobjs);
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static struct vin_device *construct_vin_device(struct gk20a *g, void *pargs);
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static u32 vin_device_init_pmudata_super(struct gk20a *g,
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struct boardobj *board_obj_ptr,
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struct nv_pmu_boardobj *ppmudata);
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static u32 read_vin_cal_fuse_rev(struct gk20a *g)
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{
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return fuse_vin_cal_fuse_rev_data_v(
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gk20a_readl(g, fuse_vin_cal_fuse_rev_r()));
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}
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static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g,
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u32 vin_id, u32 *slope,
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u32 *intercept)
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{
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u32 data = 0;
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u32 interceptdata = 0;
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u32 slopedata = 0;
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u32 gpc0data;
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u32 gpc0slopedata;
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u32 gpc0interceptdata;
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/* read gpc0 irrespective of vin id */
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gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
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if (gpc0data == 0xFFFFFFFF)
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return -EINVAL;
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switch (vin_id) {
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case CTRL_CLK_VIN_ID_GPC0:
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break;
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case CTRL_CLK_VIN_ID_GPC1:
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data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
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break;
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case CTRL_CLK_VIN_ID_GPC2:
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data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
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break;
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case CTRL_CLK_VIN_ID_GPC3:
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data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
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break;
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case CTRL_CLK_VIN_ID_GPC4:
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data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
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break;
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case CTRL_CLK_VIN_ID_GPC5:
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data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
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break;
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case CTRL_CLK_VIN_ID_SYS:
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case CTRL_CLK_VIN_ID_XBAR:
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case CTRL_CLK_VIN_ID_LTC:
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data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
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break;
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case CTRL_CLK_VIN_ID_SRAM:
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data = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
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break;
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default:
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return -EINVAL;
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}
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if (data == 0xFFFFFFFF)
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return -EINVAL;
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gpc0interceptdata = (fuse_vin_cal_gpc0_icpt_int_data_v(gpc0data) <<
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fuse_vin_cal_gpc0_icpt_frac_data_s()) +
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fuse_vin_cal_gpc0_icpt_frac_data_v(gpc0data);
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gpc0interceptdata = (gpc0interceptdata * 1000U) >>
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fuse_vin_cal_gpc0_icpt_frac_data_s();
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switch (vin_id) {
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case CTRL_CLK_VIN_ID_GPC0:
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break;
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case CTRL_CLK_VIN_ID_GPC1:
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case CTRL_CLK_VIN_ID_GPC2:
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case CTRL_CLK_VIN_ID_GPC3:
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case CTRL_CLK_VIN_ID_GPC4:
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case CTRL_CLK_VIN_ID_GPC5:
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case CTRL_CLK_VIN_ID_SYS:
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case CTRL_CLK_VIN_ID_XBAR:
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case CTRL_CLK_VIN_ID_LTC:
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interceptdata = (fuse_vin_cal_gpc1_delta_icpt_int_data_v(data) <<
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fuse_vin_cal_gpc1_delta_icpt_frac_data_s()) +
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fuse_vin_cal_gpc1_delta_icpt_frac_data_v(data);
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interceptdata = (interceptdata * 1000U) >>
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fuse_vin_cal_gpc1_delta_icpt_frac_data_s();
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break;
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case CTRL_CLK_VIN_ID_SRAM:
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interceptdata = (fuse_vin_cal_sram_delta_icpt_int_data_v(data) <<
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fuse_vin_cal_sram_delta_icpt_frac_data_s()) +
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fuse_vin_cal_sram_delta_icpt_frac_data_v(data);
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interceptdata = (interceptdata * 1000U) >>
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fuse_vin_cal_sram_delta_icpt_frac_data_s();
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break;
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default:
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return -EINVAL;
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}
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if (fuse_vin_cal_gpc1_delta_icpt_sign_data_v(data))
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*intercept = gpc0interceptdata - interceptdata;
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else
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*intercept = gpc0interceptdata + interceptdata;
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/* slope */
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gpc0slopedata = (fuse_vin_cal_gpc0_slope_int_data_v(gpc0data) <<
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fuse_vin_cal_gpc0_slope_frac_data_s()) +
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fuse_vin_cal_gpc0_slope_frac_data_v(gpc0data);
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gpc0slopedata = (gpc0slopedata * 1000U) >>
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fuse_vin_cal_gpc0_slope_frac_data_s();
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switch (vin_id) {
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case CTRL_CLK_VIN_ID_GPC0:
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break;
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case CTRL_CLK_VIN_ID_GPC1:
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case CTRL_CLK_VIN_ID_GPC2:
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case CTRL_CLK_VIN_ID_GPC3:
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case CTRL_CLK_VIN_ID_GPC4:
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case CTRL_CLK_VIN_ID_GPC5:
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case CTRL_CLK_VIN_ID_SYS:
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case CTRL_CLK_VIN_ID_XBAR:
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case CTRL_CLK_VIN_ID_LTC:
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case CTRL_CLK_VIN_ID_SRAM:
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slopedata =
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(fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) * 1000;
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break;
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default:
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return -EINVAL;
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}
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if (fuse_vin_cal_gpc1_delta_slope_sign_data_v(data))
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*slope = gpc0slopedata - slopedata;
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else
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*slope = gpc0slopedata + slopedata;
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return 0;
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}
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static u32 _clk_vin_devgrp_pmudatainit_super(struct gk20a *g,
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struct boardobjgrp *pboardobjgrp,
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struct nv_pmu_boardobjgrp_super *pboardobjgrppmu)
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{
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struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header *pset =
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(struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header *)
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pboardobjgrppmu;
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struct avfsvinobjs *pvin_obbj = (struct avfsvinobjs *)pboardobjgrp;
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u32 status = 0;
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gk20a_dbg_info("");
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status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu);
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pset->b_vin_is_disable_allowed = pvin_obbj->vin_is_disable_allowed;
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gk20a_dbg_info(" Done");
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return status;
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}
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static u32 _clk_vin_devgrp_pmudata_instget(struct gk20a *g,
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struct nv_pmu_boardobjgrp *pmuboardobjgrp,
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struct nv_pmu_boardobj **ppboardobjpmudata,
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u8 idx)
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{
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struct nv_pmu_clk_clk_vin_device_boardobj_grp_set *pgrp_set =
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(struct nv_pmu_clk_clk_vin_device_boardobj_grp_set *)
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pmuboardobjgrp;
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gk20a_dbg_info("");
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/*check whether pmuboardobjgrp has a valid boardobj in index*/
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if (((u32)BIT(idx) &
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pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
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return -EINVAL;
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*ppboardobjpmudata = (struct nv_pmu_boardobj *)
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&pgrp_set->objects[idx].data.board_obj;
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gk20a_dbg_info(" Done");
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return 0;
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}
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static u32 _clk_vin_devgrp_pmustatus_instget(struct gk20a *g,
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void *pboardobjgrppmu,
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struct nv_pmu_boardobj_query **ppboardobjpmustatus,
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u8 idx)
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{
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struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status *pgrp_get_status =
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(struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status *)
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pboardobjgrppmu;
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/*check whether pmuboardobjgrp has a valid boardobj in index*/
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if (((u32)BIT(idx) &
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pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0)
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return -EINVAL;
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*ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
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&pgrp_get_status->objects[idx].data.board_obj;
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return 0;
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}
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u32 clk_vin_sw_setup(struct gk20a *g)
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{
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u32 status;
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struct boardobjgrp *pboardobjgrp = NULL;
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u32 slope;
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u32 intercept;
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struct vin_device *pvindev;
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struct avfsvinobjs *pvinobjs;
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u8 i;
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gk20a_dbg_info("");
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status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_vinobjs.super);
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if (status) {
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gk20a_err(dev_from_gk20a(g),
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"error creating boardobjgrp for clk vin, statu - 0x%x",
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status);
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goto done;
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}
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pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super;
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pvinobjs = &g->clk_pmu.avfs_vinobjs;
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BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, VIN_DEVICE);
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status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
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clk, CLK, clk_vin_device, CLK_VIN_DEVICE);
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if (status) {
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gk20a_err(dev_from_gk20a(g),
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"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
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status);
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goto done;
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}
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pboardobjgrp->pmudatainit = _clk_vin_devgrp_pmudatainit_super;
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pboardobjgrp->pmudatainstget = _clk_vin_devgrp_pmudata_instget;
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pboardobjgrp->pmustatusinstget = _clk_vin_devgrp_pmustatus_instget;
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status = devinit_get_vin_device_table(g, &g->clk_pmu.avfs_vinobjs);
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if (status)
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goto done;
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/*update vin calibration to fuse */
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if (pvinobjs->calibration_rev_vbios == read_vin_cal_fuse_rev(g)) {
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BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super),
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struct vin_device *, pvindev, i) {
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slope = 0;
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intercept = 0;
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pvindev = CLK_GET_VIN_DEVICE(pvinobjs, i);
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status = read_vin_cal_slope_intercept_fuse(g,
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pvindev->id, &slope, &intercept);
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if (status) {
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gk20a_err(dev_from_gk20a(g),
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"err reading vin cal for id %x", pvindev->id);
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goto done;
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}
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if (slope != 0 && intercept != 0) {
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pvindev->slope = slope;
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pvindev->intercept = intercept;
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}
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}
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}
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status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
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&g->clk_pmu.avfs_vinobjs.super.super,
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clk, CLK, clk_vin_device, CLK_VIN_DEVICE);
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if (status) {
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gk20a_err(dev_from_gk20a(g),
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"error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
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status);
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goto done;
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}
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done:
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gk20a_dbg_info(" done status %x", status);
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return status;
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}
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u32 clk_vin_pmu_setup(struct gk20a *g)
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{
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u32 status;
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struct boardobjgrp *pboardobjgrp = NULL;
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gk20a_dbg_info("");
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pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super;
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if (!pboardobjgrp->bconstructed)
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return -EINVAL;
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status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
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gk20a_dbg_info("Done");
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return status;
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}
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static u32 devinit_get_vin_device_table(struct gk20a *g,
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struct avfsvinobjs *pvinobjs)
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{
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u32 status = 0;
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u8 *vin_table_ptr = NULL;
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struct vin_descriptor_header_10 vin_desc_table_header = { 0 };
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struct vin_descriptor_entry_10 vin_desc_table_entry = { 0 };
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u8 *vin_tbl_entry_ptr = NULL;
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u32 index = 0;
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u32 slope, intercept;
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struct vin_device vin_dev_data;
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struct vin_device *pvin_dev;
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gk20a_dbg_info("");
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vin_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
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g->bios.clock_token, VIN_TABLE);
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if (vin_table_ptr == NULL) {
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status = -1;
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goto done;
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}
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memcpy(&vin_desc_table_header, vin_table_ptr,
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sizeof(struct vin_descriptor_header_10));
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pvinobjs->calibration_rev_vbios =
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BIOS_GET_FIELD(vin_desc_table_header.flags0,
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NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION);
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pvinobjs->vin_is_disable_allowed =
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BIOS_GET_FIELD(vin_desc_table_header.flags0,
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NV_VIN_DESC_FLAGS0_DISABLE_CONTROL);
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/* VIN calibration slope: XX.YYY mV/code => XXYYY uV/code*/
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slope = ((BIOS_GET_FIELD(vin_desc_table_header.vin_cal,
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NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER) * 1000)) +
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((BIOS_GET_FIELD(vin_desc_table_header.vin_cal,
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NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION)));
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/* VIN calibration intercept: ZZZ.W mV => ZZZW00 uV */
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intercept = ((BIOS_GET_FIELD(vin_desc_table_header.vin_cal,
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NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER) * 1000)) +
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((BIOS_GET_FIELD(vin_desc_table_header.vin_cal,
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NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION) * 100));
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/* Read table entries*/
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vin_tbl_entry_ptr = vin_table_ptr + vin_desc_table_header.header_sizee;
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for (index = 0; index < vin_desc_table_header.entry_count; index++) {
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u32 vin_id;
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memcpy(&vin_desc_table_entry, vin_tbl_entry_ptr,
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sizeof(struct vin_descriptor_entry_10));
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if (vin_desc_table_entry.vin_device_type == CTRL_CLK_VIN_TYPE_DISABLED)
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continue;
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vin_id = vin_desc_table_entry.vin_device_id;
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vin_dev_data.super.type =
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(u8)vin_desc_table_entry.vin_device_type;
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vin_dev_data.id = (u8)vin_desc_table_entry.vin_device_id;
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vin_dev_data.volt_domain_vbios =
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(u8)vin_desc_table_entry.volt_domain_vbios;
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vin_dev_data.slope = slope;
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vin_dev_data.intercept = intercept;
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vin_dev_data.flls_shared_mask = 0;
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pvin_dev = construct_vin_device(g, (void *)&vin_dev_data);
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status = boardobjgrp_objinsert(&pvinobjs->super.super,
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(struct boardobj *)pvin_dev, index);
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vin_tbl_entry_ptr += vin_desc_table_header.entry_size;
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}
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done:
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gk20a_dbg_info(" done status %x", status);
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return status;
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}
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static struct vin_device *construct_vin_device(struct gk20a *g, void *pargs)
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{
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struct boardobj *board_obj_ptr = NULL;
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struct vin_device *pvin_dev;
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struct vin_device *board_obj_vin_ptr = NULL;
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u32 status;
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gk20a_dbg_info("");
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status = boardobj_construct_super(g, &board_obj_ptr,
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sizeof(struct vin_device), pargs);
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if (status)
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return NULL;
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/*got vin board obj allocated now fill it into boardobj grp*/
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pvin_dev = (struct vin_device *)pargs;
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board_obj_vin_ptr = (struct vin_device *)board_obj_ptr;
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/* override super class interface */
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board_obj_ptr->pmudatainit = vin_device_init_pmudata_super;
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board_obj_vin_ptr->id = pvin_dev->id;
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board_obj_vin_ptr->volt_domain_vbios = pvin_dev->volt_domain_vbios;
|
|
board_obj_vin_ptr->slope = pvin_dev->slope;
|
|
board_obj_vin_ptr->intercept = pvin_dev->intercept;
|
|
board_obj_vin_ptr->flls_shared_mask = pvin_dev->flls_shared_mask;
|
|
board_obj_vin_ptr->volt_domain = CTRL_VOLT_DOMAIN_LOGIC;
|
|
|
|
gk20a_dbg_info(" Done");
|
|
|
|
return (struct vin_device *)board_obj_ptr;
|
|
}
|
|
|
|
static u32 vin_device_init_pmudata_super(struct gk20a *g,
|
|
struct boardobj *board_obj_ptr,
|
|
struct nv_pmu_boardobj *ppmudata)
|
|
{
|
|
u32 status = 0;
|
|
struct vin_device *pvin_dev;
|
|
struct nv_pmu_clk_clk_vin_device_boardobj_set *perf_pmu_data;
|
|
|
|
gk20a_dbg_info("");
|
|
|
|
status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
|
|
if (status != 0)
|
|
return status;
|
|
|
|
pvin_dev = (struct vin_device *)board_obj_ptr;
|
|
perf_pmu_data = (struct nv_pmu_clk_clk_vin_device_boardobj_set *)
|
|
ppmudata;
|
|
|
|
perf_pmu_data->id = pvin_dev->id;
|
|
perf_pmu_data->intercept = pvin_dev->intercept;
|
|
perf_pmu_data->volt_domain = pvin_dev->volt_domain;
|
|
perf_pmu_data->slope = pvin_dev->slope;
|
|
perf_pmu_data->flls_shared_mask = pvin_dev->flls_shared_mask;
|
|
|
|
gk20a_dbg_info(" Done");
|
|
|
|
return status;
|
|
}
|