Seema Khowala 56eaeab512 gpu: nvgpu: gv11b: sm stride litter added ...

Required to support multiple SM

JIRA GPUT19X-75

Change-Id: I1fd0530550ae14270a5e746d2efbf3e913ac4c3e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1475985
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>

2017-06-29 13:28:53 -07:00

..

bus_gv11b.c

gpu: nvgpu: Add bus HAL

2017-03-23 08:44:12 -07:00

bus_gv11b.h

gpu: nvgpu: Add bus HAL

2017-03-23 08:44:12 -07:00

ce_gv11b.c

nvgpu: gpu: HW header update for Volta

2017-01-24 15:15:16 -08:00

ce_gv11b.h

gpu: nvgpu: Add multiple engine and runlist support

2016-06-07 12:31:40 -07:00

ecc_gv11b.h

gpu: nvgpu: add chip specific ECC counters

2017-06-04 20:34:58 -07:00

fb_gv11b.c

gpu: nvgpu: gv11b: fbhub: num_ltcs are read only

2017-06-21 15:24:35 -07:00

fb_gv11b.h

gpu: nvgpu: gv11b: MMU parity HWW error intr

2017-05-11 06:04:33 -07:00

fecs_trace_gv11b.c

nvgpu: gpu: HW header update for Volta

2017-01-24 15:15:16 -08:00

fecs_trace_gv11b.h

gpu: nvgpu: gv11b: sm priv reg related changes

2016-04-16 07:48:28 -07:00

fifo_gv11b.c

gpu: nvgpu: gv11b: implement ctxnotvalid pbdma_intr_1

2017-06-27 03:56:54 -07:00

fifo_gv11b.h

gpu: nvgpu: gv11b: init handle sched_error & ctxsw_timout ops

2017-04-12 15:33:50 -07:00

gr_ctx_gv11b.c

nvgpu: gpu: HW header update for Volta

2017-01-24 15:15:16 -08:00

gr_ctx_gv11b.h

gpu: nvgpu: gv11b: Don't set net name for pri-silicon

2017-05-29 12:23:21 -07:00

gr_gv11b.c

gpu: nvgpu: gv11b: sw method for NVC397_SET_TEX_IN_DBG

2017-06-27 10:44:05 -07:00

gr_gv11b.h

gpu: nvgpu: gv11b: sw method for NVC397_SET_TEX_IN_DBG

2017-06-27 10:44:05 -07:00

gv11b_gating_reglist.c

gpu: nvgpu: gv11b: update clock gating prod settings

2017-01-27 10:53:26 -08:00

gv11b_gating_reglist.h

gpu: nvgpu: gv11b: add clock gating prod settings

2016-12-21 12:38:20 -08:00

gv11b.c

nvgpu: gpu: HW header update for Volta

2017-01-24 15:15:16 -08:00

gv11b.h

gpu: nvgpu: gv11b: sm priv reg related changes

2016-04-16 07:48:28 -07:00

hal_gv11b.c

gpu: nvgpu: gv11b: sm stride litter added

2017-06-29 13:28:53 -07:00

hal_gv11b.h

gpu: nvgpu: gv11b: added initial source code

2016-04-13 08:15:13 -07:00

ltc_gv11b.c

gpu: nvgpu: Reorganize ltc HAL initialization

2017-06-27 10:44:06 -07:00

ltc_gv11b.h

gpu: nvgpu: Reorganize ltc HAL initialization

2017-06-27 10:44:06 -07:00

mc_gv11b.c

gpu: nvgpu: gv11b: MMU parity HWW error intr

2017-05-11 06:04:33 -07:00

mc_gv11b.h

gpu: nvgpu: gv11b: added initial source code

2016-04-13 08:15:13 -07:00

mm_gv11b.c

gpu: nvgpu: gv11b: fb_flush before/after l2_flush

2017-06-20 10:25:32 -07:00

mm_gv11b.h

gpu: nvgpu: gv11b: sm priv reg related changes

2016-04-16 07:48:28 -07:00

platform_gv11b_tegra.c

gpu: nvgpu: gv11b: enable sync point support

2017-06-27 03:56:52 -07:00

pmu_gv11b.c

gpu: nvgpu: gv11b, use nvgpu_flcn_copy_to_dmem()

2017-06-27 03:58:21 -07:00

pmu_gv11b.h

gpu: nvgpu: gv11b: sm priv reg related changes

2016-04-16 07:48:28 -07:00

regops_gv11b.c

gpu: nvgpu: gv11b: update regops whitelist

2017-06-01 10:13:57 -07:00

regops_gv11b.h

gpu: nvgpu: gv11b: add regops whitelists

2017-01-27 17:29:57 -08:00

subctx_gv11b.c

gpu: nvgpu: gv11b: make subcontext mappings non-cacheable

2017-06-20 10:25:32 -07:00

subctx_gv11b.h

gpu: nvgpu: gv11b: function to get max veid

2017-04-16 17:54:07 -07:00

therm_gv11b.c

nvgpu: gpu: HW header update for Volta

2017-01-24 15:15:16 -08:00

therm_gv11b.h

gpu: nvgpu: gv11b: sm priv reg related changes

2016-04-16 07:48:28 -07:00