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7633cf41fb
This "HAL" exists to handle the vGPU specific bind channel operation. This patch moves the native function implementation to common/mm/vm.c and renames the gk20a to nvgpu to follow the convention for vGPU vs native HAL functions. JIRA NVGPU-2042 Change-Id: I02b9ebf0d53d58a6d2ede544e34f2b8ff1b1eb42 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2104540 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef MM_GK20A_H
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#define MM_GK20A_H
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/allocator.h>
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#include <nvgpu/vm.h>
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#include <nvgpu/list.h>
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#include <nvgpu/rbtree.h>
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#include <nvgpu/kref.h>
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struct compbit_store_desc {
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struct nvgpu_mem mem;
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/* The value that is written to the hardware. This depends on
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* on the number of ltcs and is not an address. */
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u64 base_hw;
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};
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struct gk20a_buffer_state {
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struct nvgpu_list_node list;
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/* The valid compbits and the fence must be changed atomically. */
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struct nvgpu_mutex lock;
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/* Offset of the surface within the dma-buf whose state is
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* described by this struct (one dma-buf can contain multiple
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* surfaces with different states). */
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size_t offset;
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/* A bitmask of valid sets of compbits (0 = uncompressed). */
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u32 valid_compbits;
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/* The ZBC color used on this buffer. */
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u32 zbc_color;
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/* This struct reflects the state of the buffer when this
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* fence signals. */
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struct nvgpu_fence_type *fence;
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};
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static inline struct gk20a_buffer_state *
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gk20a_buffer_state_from_list(struct nvgpu_list_node *node)
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{
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return (struct gk20a_buffer_state *)
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((uintptr_t)node - offsetof(struct gk20a_buffer_state, list));
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};
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struct gk20a;
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struct channel_gk20a;
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#define dev_from_vm(vm) dev_from_gk20a(vm->mm->g)
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void gk20a_mm_ltc_isr(struct gk20a *g);
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bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g);
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int gk20a_alloc_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block);
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void gk20a_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
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u32 big_page_size);
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int gk20a_init_mm_setup_hw(struct gk20a *g);
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/* vm-as interface */
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struct nvgpu_as_alloc_space_args;
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struct nvgpu_as_free_space_args;
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int gk20a_vm_release_share(struct gk20a_as_share *as_share);
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void pde_range_from_vaddr_range(struct vm_gk20a *vm,
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u64 addr_lo, u64 addr_hi,
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u32 *pde_lo, u32 *pde_hi);
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u32 gk20a_mm_get_iommu_bit(struct gk20a *g);
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u64 gk20a_mm_bar1_map_userd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset);
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#endif /* MM_GK20A_H */
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