mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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589d6385b1
Move clock APIs from gk20a_platform to gpu_ops. At the same time allow use of internal get_rate/set_rate for querying both GPCCLK and PWRCLK on iGPU. At the same time we can replace calls to clk framework with the new HAL and drop direct dependency to clk framework. gp10b ops were replaced as a whole at HAL initialization. That replaces anything set in platform probe stage, so reduce that to touch only clock gating regs. Change-Id: Iaf219b1f000d362dbf397d45832f52d25463b31c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300113 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
183 lines
4.7 KiB
C
183 lines
4.7 KiB
C
/*
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* drivers/video/tegra/host/gk20a/hal_gk20a.c
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*
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* GK20A Tegra HAL interface.
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*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "hal_gk20a.h"
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#include "ltc_gk20a.h"
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#include "fb_gk20a.h"
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#include "gk20a.h"
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#include "gk20a_gating_reglist.h"
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#include "channel_gk20a.h"
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#include "gr_ctx_gk20a.h"
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#include "fecs_trace_gk20a.h"
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#include "mm_gk20a.h"
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#include "mc_gk20a.h"
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#include "pmu_gk20a.h"
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#include "clk_gk20a.h"
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#include "regops_gk20a.h"
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#include "therm_gk20a.h"
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#include "tsg_gk20a.h"
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#include "dbg_gpu_gk20a.h"
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#include "css_gr_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_proj_gk20a.h>
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static struct gpu_ops gk20a_ops = {
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.clock_gating = {
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.slcg_gr_load_gating_prod =
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gr_gk20a_slcg_gr_load_gating_prod,
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.slcg_perf_load_gating_prod =
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gr_gk20a_slcg_perf_load_gating_prod,
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.slcg_ltc_load_gating_prod =
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ltc_gk20a_slcg_ltc_load_gating_prod,
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.blcg_gr_load_gating_prod =
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gr_gk20a_blcg_gr_load_gating_prod,
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.pg_gr_load_gating_prod =
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gr_gk20a_pg_gr_load_gating_prod,
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.slcg_therm_load_gating_prod =
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gr_gk20a_slcg_therm_load_gating_prod,
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},
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};
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static int gk20a_get_litter_value(struct gk20a *g, int value)
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{
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int ret = EINVAL;
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switch (value) {
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case GPU_LIT_NUM_GPCS:
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ret = proj_scal_litter_num_gpcs_v();
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break;
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case GPU_LIT_NUM_PES_PER_GPC:
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ret = proj_scal_litter_num_pes_per_gpc_v();
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break;
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case GPU_LIT_NUM_ZCULL_BANKS:
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ret = proj_scal_litter_num_zcull_banks_v();
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break;
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case GPU_LIT_NUM_TPC_PER_GPC:
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ret = proj_scal_litter_num_tpc_per_gpc_v();
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break;
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case GPU_LIT_NUM_FBPS:
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ret = proj_scal_litter_num_fbps_v();
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break;
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case GPU_LIT_GPC_BASE:
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ret = proj_gpc_base_v();
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break;
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case GPU_LIT_GPC_STRIDE:
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ret = proj_gpc_stride_v();
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break;
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case GPU_LIT_GPC_SHARED_BASE:
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ret = proj_gpc_shared_base_v();
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break;
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case GPU_LIT_TPC_IN_GPC_BASE:
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ret = proj_tpc_in_gpc_base_v();
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break;
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case GPU_LIT_TPC_IN_GPC_STRIDE:
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ret = proj_tpc_in_gpc_stride_v();
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break;
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case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
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ret = proj_tpc_in_gpc_shared_base_v();
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break;
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case GPU_LIT_PPC_IN_GPC_BASE:
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ret = proj_ppc_in_gpc_base_v();
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break;
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case GPU_LIT_PPC_IN_GPC_STRIDE:
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ret = proj_ppc_in_gpc_stride_v();
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break;
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case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
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ret = proj_ppc_in_gpc_shared_base_v();
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break;
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case GPU_LIT_ROP_BASE:
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ret = proj_rop_base_v();
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break;
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case GPU_LIT_ROP_STRIDE:
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ret = proj_rop_stride_v();
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break;
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case GPU_LIT_ROP_SHARED_BASE:
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ret = proj_rop_shared_base_v();
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break;
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case GPU_LIT_HOST_NUM_ENGINES:
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ret = proj_host_num_engines_v();
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break;
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case GPU_LIT_HOST_NUM_PBDMA:
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ret = proj_host_num_pbdma_v();
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break;
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case GPU_LIT_LTC_STRIDE:
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ret = proj_ltc_stride_v();
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break;
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case GPU_LIT_LTS_STRIDE:
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ret = proj_lts_stride_v();
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break;
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/* GK20A does not have a FBPA unit, despite what's listed in the
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* hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS,
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* so hardcode all values to 0.
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*/
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case GPU_LIT_NUM_FBPAS:
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case GPU_LIT_FBPA_STRIDE:
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case GPU_LIT_FBPA_BASE:
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case GPU_LIT_FBPA_SHARED_BASE:
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ret = 0;
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break;
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default:
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gk20a_err(dev_from_gk20a(g), "Missing definition %d", value);
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BUG();
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break;
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}
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return ret;
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}
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int gk20a_init_hal(struct gk20a *g)
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{
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struct gpu_ops *gops = &g->ops;
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struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
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gops->clock_gating = gk20a_ops.clock_gating;
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gops->privsecurity = 0;
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gops->securegpccs = 0;
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gops->pmupstate = false;
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gk20a_init_mc(gops);
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gk20a_init_ltc(gops);
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gk20a_init_gr_ops(gops);
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gk20a_init_fecs_trace_ops(gops);
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gk20a_init_fb(gops);
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gk20a_init_fifo(gops);
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gk20a_init_ce2(gops);
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gk20a_init_gr_ctx(gops);
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gk20a_init_mm(gops);
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gk20a_init_pmu_ops(gops);
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gk20a_init_clk_ops(gops);
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gk20a_init_regops(gops);
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gk20a_init_debug_ops(gops);
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gk20a_init_dbg_session_ops(gops);
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gk20a_init_therm_ops(gops);
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gk20a_init_tsg_ops(gops);
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#if defined(CONFIG_GK20A_CYCLE_STATS)
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gk20a_init_css_ops(gops);
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#endif
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gops->name = "gk20a";
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gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
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gops->get_litter_value = gk20a_get_litter_value;
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gops->read_ptimer = gk20a_read_ptimer;
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c->twod_class = FERMI_TWOD_A;
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c->threed_class = KEPLER_C;
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c->compute_class = KEPLER_COMPUTE_A;
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c->gpfifo_class = KEPLER_CHANNEL_GPFIFO_C;
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c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_A;
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c->dma_copy_class = KEPLER_DMA_COPY_A;
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return 0;
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}
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