Thomas Fleury 5e9bdbc80d gpu: nvgpu: runlist update timeout in safety ...

Runlist update occurs in non-mission mode, when
adding/removing channel/TSGs. The pending bit
is a debug only feature. As a result logging a
warning is sufficient.

We expect other HW safety mechanisms such as
PBDMA timeout to detect issues that caused pending
to not clear. It's possible bad base address could
cause some MMU faults too.

Worst case we rely on the application level task
monitor to detect the GPU tasks are not completing
on time.

Jira NVGPU-4322

Change-Id: I7233770349db5dfad6904170a1e9a2d5eada70b2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265094
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2020-12-15 14:10:29 -06:00

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