linux-nvgpu/drivers/gpu/nvgpu/hal/fifo/pbdma_gp10b.c

/*
 * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <nvgpu/types.h>
#include <nvgpu/gk20a.h>

#include <nvgpu/hw/gp10b/hw_pbdma_gp10b.h>

#include "pbdma_gp10b.h"

u32 gp10b_pbdma_get_signature(struct gk20a *g)
{
	return g->ops.get_litter_value(g, GPU_LIT_GPFIFO_CLASS)
		| pbdma_signature_sw_zero_f();
}

u32 gp10b_pbdma_channel_fatal_0_intr_descs(void)
{
	/*
	 * These are data parsing, framing errors or others which can be
	 * recovered from with intervention... or just resetting the
	 * channel
	 */
	u32 channel_fatal_0_intr_descs =
		pbdma_intr_0_gpfifo_pending_f() |
		pbdma_intr_0_gpptr_pending_f() |
		pbdma_intr_0_gpentry_pending_f() |
		pbdma_intr_0_gpcrc_pending_f() |
		pbdma_intr_0_pbptr_pending_f() |
		pbdma_intr_0_pbentry_pending_f() |
		pbdma_intr_0_pbcrc_pending_f() |
		pbdma_intr_0_method_pending_f() |
		pbdma_intr_0_methodcrc_pending_f() |
		pbdma_intr_0_pbseg_pending_f() |
		pbdma_intr_0_syncpoint_illegal_pending_f() |
		pbdma_intr_0_signature_pending_f();

	return channel_fatal_0_intr_descs;
}

u32 gp10b_pbdma_get_fc_runlist_timeslice(void)
{
	return (pbdma_runlist_timeslice_timeout_128_f() |
		pbdma_runlist_timeslice_timescale_3_f() |
		pbdma_runlist_timeslice_enable_true_f());
}

u32 gp10b_pbdma_get_config_auth_level_privileged(void)
{
	return pbdma_config_auth_level_privileged_f();
}

u32 gp10b_pbdma_allowed_syncpoints_0_index_f(u32 syncpt)
{
	return pbdma_allowed_syncpoints_0_index_f(syncpt);
}

u32 gp10b_pbdma_allowed_syncpoints_0_valid_f(void)
{
	return pbdma_allowed_syncpoints_0_valid_f(1);
}

u32 gp10b_pbdma_allowed_syncpoints_0_index_v(u32 offset)
{
	return pbdma_allowed_syncpoints_0_index_v(offset);
}