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650171566b
For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. On gv100 the registers GPM_PD_SM_ID and SM_CFG are indexed on nonpes aware tpc. Bug 2096878 Change-Id: I0edc2f066e2c3b35057fde102689a9f1915c72ea Signed-off-by: Philemon Gardet <pgardet@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1783046 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Sandarbh Jain <sanjain@nvidia.com> Tested-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>