sujeet baranwal 6ceef08d52 gpu: nvgpu: Add CDE bits in FECS header ...

In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B
aligned, otherwise causes a HW deadlock. Gpu driver makes changes in
FECS header which FECS uses to configure the T1 promotions to aligned
128B accesses.

Bug 200096226

Change-Id: Ic006b2c7035bbeabe1081aeed968a6c6d11f9995
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/802327
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

2015-09-24 07:53:43 -07:00

..

gk20a

gpu: nvgpu: Add CDE bits in FECS header

2015-09-24 07:53:43 -07:00

gm20b

gpu: nvgpu: Add CDE bits in FECS header

2015-09-24 07:53:43 -07:00

vgpu

gpu: nvgpu: Separate kernel and user GPU VA regions

2015-09-07 12:37:15 -07:00

Kconfig

gpu: nvgpu: Set default timeout to 5s

2015-04-04 19:01:14 -07:00

Makefile

gpu: nvgpu: Prepare for per-GPU CDE program numbers

2015-08-19 08:03:24 -07:00

platform_tegra.h

gpu: nvgpu: Export VPR allocator

2015-05-05 13:59:06 -07:00