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The simulator ring buffer DMA interface supports buffers of the following sizes: 4, 8, 12 and 16K. At present, it is configured to 4K and it happens to match with the kernel PAGE_SIZE, which is used to wrap back the GET/PUT pointers once 4K is reached. However, this is not always true; for instance, take 64K pages. Hence, replace PAGE_SIZE with SIM_BFR_SIZE. Introduce macro NVGPU_CPU_PAGE_SIZE which aliases to PAGE_SIZE and replace latter with former. Bug 200658101 Jira NVGPU-6018 Change-Id: I83cc62b87291734015c51f3e5a98173549e065de Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420728 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
158 lines
4.1 KiB
C
158 lines
4.1 KiB
C
/*
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* USERD
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*
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* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/trace.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/fifo/userd.h>
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#include <nvgpu/vm_area.h>
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#include <nvgpu/dma.h>
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int nvgpu_userd_init_slabs(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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int err;
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nvgpu_mutex_init(&f->userd_mutex);
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f->num_channels_per_slab = NVGPU_CPU_PAGE_SIZE / g->ops.userd.entry_size(g);
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f->num_userd_slabs =
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DIV_ROUND_UP(f->num_channels, f->num_channels_per_slab);
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f->userd_slabs = nvgpu_big_zalloc(g, f->num_userd_slabs *
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sizeof(struct nvgpu_mem));
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if (f->userd_slabs == NULL) {
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nvgpu_err(g, "could not allocate userd slabs");
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err = -ENOMEM;
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goto clean_up;
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}
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return 0;
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clean_up:
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nvgpu_mutex_destroy(&f->userd_mutex);
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return err;
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}
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void nvgpu_userd_free_slabs(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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u32 slab;
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for (slab = 0; slab < f->num_userd_slabs; slab++) {
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nvgpu_dma_free(g, &f->userd_slabs[slab]);
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}
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nvgpu_big_free(g, f->userd_slabs);
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f->userd_slabs = NULL;
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nvgpu_mutex_destroy(&f->userd_mutex);
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}
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int nvgpu_userd_init_channel(struct gk20a *g, struct nvgpu_channel *c)
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{
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struct nvgpu_fifo *f = &g->fifo;
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struct nvgpu_mem *mem;
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u32 slab = c->chid / f->num_channels_per_slab;
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int err = 0;
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if (slab > f->num_userd_slabs) {
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nvgpu_err(g, "chid %u, slab %u out of range (max=%u)",
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c->chid, slab, f->num_userd_slabs);
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return -EINVAL;
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}
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mem = &g->fifo.userd_slabs[slab];
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nvgpu_mutex_acquire(&f->userd_mutex);
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if (!nvgpu_mem_is_valid(mem)) {
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err = nvgpu_dma_alloc_sys(g, NVGPU_CPU_PAGE_SIZE, mem);
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if (err != 0) {
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nvgpu_err(g, "userd allocation failed, err=%d", err);
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goto done;
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}
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if (g->ops.mm.is_bar1_supported(g)) {
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mem->gpu_va = g->ops.mm.bar1_map_userd(g, mem,
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slab * NVGPU_CPU_PAGE_SIZE);
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}
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}
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c->userd_mem = mem;
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c->userd_offset = (c->chid % f->num_channels_per_slab) *
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g->ops.userd.entry_size(g);
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c->userd_iova = nvgpu_channel_userd_addr(c);
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nvgpu_log(g, gpu_dbg_info,
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"chid=%u slab=%u mem=%p offset=%u addr=%llx gpu_va=%llx",
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c->chid, slab, mem, c->userd_offset,
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nvgpu_channel_userd_addr(c),
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nvgpu_channel_userd_gpu_va(c));
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done:
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nvgpu_mutex_release(&f->userd_mutex);
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return err;
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}
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int nvgpu_userd_setup_sw(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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int err;
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u32 size, num_pages;
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err = nvgpu_userd_init_slabs(g);
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if (err != 0) {
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nvgpu_err(g, "failed to init userd support");
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return err;
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}
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size = f->num_channels * g->ops.userd.entry_size(g);
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num_pages = DIV_ROUND_UP(size, NVGPU_CPU_PAGE_SIZE);
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err = nvgpu_vm_area_alloc(g->mm.bar1.vm,
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num_pages, NVGPU_CPU_PAGE_SIZE, &f->userd_gpu_va, 0);
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if (err != 0) {
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nvgpu_err(g, "userd gpu va allocation failed, err=%d", err);
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goto clean_up;
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}
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return 0;
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clean_up:
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nvgpu_userd_free_slabs(g);
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return err;
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}
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void nvgpu_userd_cleanup_sw(struct gk20a *g)
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{
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struct nvgpu_fifo *f = &g->fifo;
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if (f->userd_gpu_va != 0ULL) {
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(void) nvgpu_vm_area_free(g->mm.bar1.vm, f->userd_gpu_va);
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f->userd_gpu_va = 0ULL;
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}
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nvgpu_userd_free_slabs(g);
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}
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