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d3fef630f5
Rule 8.6 requires each identifier with external linkage to have exactly one external definitions. This patch fixes 8.6 issues in nvgpu/hal/fifo/ pbdma_gm20b.h Jira NVGPU-3822 Change-Id: I601c5ba65fe282a04d1c85a5e20318a1d9d9a44f Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2154400 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
82 lines
3.2 KiB
C
82 lines
3.2 KiB
C
/*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PBDMA_GM20B_H
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#define NVGPU_PBDMA_GM20B_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_debug_context;
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struct nvgpu_channel_dump_info;
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struct nvgpu_gpfifo_entry;
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bool gm20b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_intr_0, u32 *error_notifier);
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bool gm20b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id,
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u32 *error_notifier);
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u32 gm20b_pbdma_read_data(struct gk20a *g, u32 pbdma_id);
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void gm20b_pbdma_reset_header(struct gk20a *g, u32 pbdma_id);
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void gm20b_pbdma_reset_method(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_method_index);
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u32 gm20b_pbdma_acquire_val(u64 timeout);
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void gm20b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o);
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void gm20b_pbdma_format_gpfifo_entry(struct gk20a *g,
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struct nvgpu_gpfifo_entry *gpfifo_entry,
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u64 pb_gpu_va, u32 method_size);
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u32 gm20b_pbdma_device_fatal_0_intr_descs(void);
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u32 gm20b_pbdma_restartable_0_intr_descs(void);
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void gm20b_pbdma_clear_all_intr(struct gk20a *g, u32 pbdma_id);
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void gm20b_pbdma_disable_and_clear_all_intr(struct gk20a *g);
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u32 gm20b_pbdma_get_gp_base(u64 gpfifo_base);
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u32 gm20b_pbdma_get_gp_base_hi(u64 gpfifo_base, u32 gpfifo_entry);
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u32 gm20b_pbdma_get_fc_subdevice(void);
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u32 gm20b_pbdma_get_fc_target(void);
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u32 gm20b_pbdma_get_ctrl_hce_priv_mode_yes(void);
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u32 gm20b_pbdma_get_userd_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem);
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u32 gm20b_pbdma_get_userd_addr(u32 addr_lo);
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u32 gm20b_pbdma_get_userd_hi_addr(u32 addr_hi);
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#ifdef CONFIG_NVGPU_HAL_NON_FUSA
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void gm20b_pbdma_intr_enable(struct gk20a *g, bool enable);
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bool gm20b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_intr_1, u32 *error_notifier);
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u32 gm20b_pbdma_get_signature(struct gk20a *g);
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u32 gm20b_pbdma_channel_fatal_0_intr_descs(void);
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void gm20b_pbdma_syncpoint_debug_dump(struct gk20a *g,
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struct nvgpu_debug_context *o,
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struct nvgpu_channel_dump_info *info);
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void gm20b_pbdma_setup_hw(struct gk20a *g);
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u32 gm20b_pbdma_get_fc_formats(void);
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u32 gm20b_pbdma_get_fc_pb_header(void);
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#endif
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#endif /* NVGPU_PBDMA_GM20B_H */
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