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On all chips except ga10b, the number of ROP, L2 units per FBP were in sync, hence, their FS masks could be represented by a single fuse register NV_FUSE_STATUS_OPT_ROP_L2_FBP. However, on ga10b, the ROP unit was moved out from FBP to GPC and it no longer matches the number of L2 units, so the previous fuse register was broken into two - NV_FUSE_CTRL_OPT_LTC_FBP, NV_FUSE_CTRL_OPT_ROP_GPC. At present, the driver reads the NV_FUSE_CTRL_OPT_ROP_GPC register and reports incorrect L2 mask. Introduce HAL function ga10b_fuse_status_opt_l2_fbp to fix this. In addition, rename fields and functions to exclusively fetch L2 masks, this should help accommadate ga10b and future chips in which L2 and ROP units are not in same. As part of this, the following functions and fields have been renamed. - nvgpu_fbp_get_rop_l2_en_mask => nvgpu_fbp_get_l2_en_mask - fuse.fuse_status_opt_rop_l2_fbp => fuse.fuse_status_opt_l2_fbp - nvgpu_fbp.fbp_rop_l2_en_mask => nvgpu_fbp.fbp_l2_en_mask The HAL ga10b_fuse_status_opt_rop_gpc is removed as rop mask is not used anywhere in the driver nor exposed to userspace. Bug 200737717 Bug 200747149 Change-Id: If40fe7ecd1f47c23f7683369a60d8dd686590ca4 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551998 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>