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f51a43b579
On all chips except ga10b, the number of ROP, L2 units per FBP were in sync, hence, their FS masks could be represented by a single fuse register NV_FUSE_STATUS_OPT_ROP_L2_FBP. However, on ga10b, the ROP unit was moved out from FBP to GPC and it no longer matches the number of L2 units, so the previous fuse register was broken into two - NV_FUSE_CTRL_OPT_LTC_FBP, NV_FUSE_CTRL_OPT_ROP_GPC. At present, the driver reads the NV_FUSE_CTRL_OPT_ROP_GPC register and reports incorrect L2 mask. Introduce HAL function ga10b_fuse_status_opt_l2_fbp to fix this. In addition, rename fields and functions to exclusively fetch L2 masks, this should help accommadate ga10b and future chips in which L2 and ROP units are not in same. As part of this, the following functions and fields have been renamed. - nvgpu_fbp_get_rop_l2_en_mask => nvgpu_fbp_get_l2_en_mask - fuse.fuse_status_opt_rop_l2_fbp => fuse.fuse_status_opt_l2_fbp - nvgpu_fbp.fbp_rop_l2_en_mask => nvgpu_fbp.fbp_l2_en_mask The HAL ga10b_fuse_status_opt_rop_gpc is removed as rop mask is not used anywhere in the driver nor exposed to userspace. Bug 200737717 Bug 200747149 Change-Id: If40fe7ecd1f47c23f7683369a60d8dd686590ca4 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551998 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
131 lines
3.4 KiB
C
131 lines
3.4 KiB
C
/*
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* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/log.h>
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#include <nvgpu/fbp.h>
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#include <nvgpu/static_analysis.h>
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#include "fbp_priv.h"
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int nvgpu_fbp_init_support(struct gk20a *g)
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{
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struct nvgpu_fbp *fbp;
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u32 fbp_en_mask;
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#ifdef CONFIG_NVGPU_NON_FUSA
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u32 max_ltc_per_fbp;
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u32 l2_all_en_mask;
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unsigned long i;
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unsigned long fbp_en_mask_tmp;
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u32 tmp;
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#endif
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if (g->fbp != NULL) {
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return 0;
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}
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fbp = nvgpu_kzalloc(g, sizeof(*fbp));
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if (fbp == NULL) {
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return -ENOMEM;
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}
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#ifdef CONFIG_NVGPU_NON_FUSA
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fbp->num_fbps = g->ops.priv_ring.get_fbp_count(g);
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nvgpu_log_info(g, "fbps: %d", fbp->num_fbps);
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#endif
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fbp->max_fbps_count = g->ops.top.get_max_fbps_count(g);
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nvgpu_log_info(g, "max_fbps_count: %d", fbp->max_fbps_count);
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/*
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* Read active fbp mask from fuse
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* Note that 0:enable and 1:disable in value read from fuse so we've to
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* flip the bits.
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* Also set unused bits to zero
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*/
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fbp_en_mask = g->ops.fuse.fuse_status_opt_fbp(g);
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fbp_en_mask = ~fbp_en_mask;
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fbp_en_mask = fbp_en_mask &
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nvgpu_safe_sub_u32(BIT32(fbp->max_fbps_count), 1U);
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fbp->fbp_en_mask = fbp_en_mask;
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#ifdef CONFIG_NVGPU_NON_FUSA
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fbp->fbp_l2_en_mask =
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nvgpu_kzalloc(g,
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nvgpu_safe_mult_u64(fbp->max_fbps_count, sizeof(u32)));
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if (fbp->fbp_l2_en_mask == NULL) {
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nvgpu_kfree(g, fbp);
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return -ENOMEM;
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}
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fbp_en_mask_tmp = fbp_en_mask;
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max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g);
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l2_all_en_mask = nvgpu_safe_sub_u32(BIT32(max_ltc_per_fbp), 1U);
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/* get active L2 mask per FBP */
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for_each_set_bit(i, &fbp_en_mask_tmp, fbp->max_fbps_count) {
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tmp = g->ops.fuse.fuse_status_opt_l2_fbp(g, i);
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fbp->fbp_l2_en_mask[i] = l2_all_en_mask ^ tmp;
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}
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#endif
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g->fbp = fbp;
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return 0;
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}
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void nvgpu_fbp_remove_support(struct gk20a *g)
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{
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struct nvgpu_fbp *fbp = g->fbp;
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if (fbp != NULL) {
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nvgpu_kfree(g, fbp->fbp_l2_en_mask);
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nvgpu_kfree(g, fbp);
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}
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g->fbp = NULL;
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}
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u32 nvgpu_fbp_get_max_fbps_count(struct nvgpu_fbp *fbp)
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{
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return fbp->max_fbps_count;
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}
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u32 nvgpu_fbp_get_fbp_en_mask(struct nvgpu_fbp *fbp)
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{
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return fbp->fbp_en_mask;
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}
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#ifdef CONFIG_NVGPU_NON_FUSA
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u32 nvgpu_fbp_get_num_fbps(struct nvgpu_fbp *fbp)
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{
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return fbp->num_fbps;
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}
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u32 *nvgpu_fbp_get_l2_en_mask(struct nvgpu_fbp *fbp)
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{
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return fbp->fbp_l2_en_mask;
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}
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#endif
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